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公开(公告)号:AU2003296523A8
公开(公告)日:2004-06-30
申请号:AU2003296523
申请日:2003-12-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor: LAUTERBACH CHRISTL , STURM THOMAS , WEBER WERNER , JUNG STEFAN , STOHR ANNELIE , STROMBERG GUIDO
Abstract: The invention relates to a surface paneling module that includes a power supply connection and a data transfer interface as well as a processor that is coupled to the power supply connection and the data transfer
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公开(公告)号:DE10227850A1
公开(公告)日:2004-01-15
申请号:DE10227850
申请日:2002-06-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor: LUYKEN JOHANNES R , SEITZ MARKUS , PREECE JON , WEBER WERNER , SCHMID GUENTER
IPC: C07D213/22 , G11C13/02 , H01L27/28 , H01L51/30 , H01L51/20 , H01L51/40 , H01L51/00 , G11C11/21 , C07D213/00
Abstract: A circuit element comprises a monomolecular layer of redox-active bis-pyridinium molecules situated between the first and second conductive layers, whereby the bis-pyridinium molecules of the monomolecular layer are immobilized on the electrically conductive layer as at least one discrete region. A circuit element (I) comprises a first layer of an electrically insulating substrate material with a first electrically conductive material comprising at least one discrete region that is embedded into or applied onto the substrate; a second layer with a second electrically conductive material and a monomolecular layer of redox-active bis-pyridinium molecules situated between the first and second layers, whereby the bis-pyridinium molecules of the monomolecular layer are immobilized on the electrically conductive layer as at least one discrete region and are in electrical contact with the second electrical material of the second layer and electrically inert molecules are immobilized on the first layer to form a matrix that surrounds at least one discrete region of the monomolecular layer of bispyridinium molecules. Independent claims are included for: (1) a process for the production of a circuit element (I) by application and/or embedding of a first electrically conductive material to at least one discrete position on/in the substrate material; immobilization of a monomolecular layer of redox-active bispyridinium molecules onto at least one discrete region of the first electrically conductive material; immobilization of electrically inert molecules onto the first layer of electrically insulating material that surround at least one region with the monomolecular layer of bis-pyridinium molecules; application of a second layer with a second electrically conductive material onto the layer of the electrically inert molecules and the bis-pyridinium molecules, whereby the bispyridinium molecules of the monomolecular layer are in contact with the second electrically material of the second layer; (2) bispyridinium compounds of formula (1) with the exclusion of N,N'-dimethyl-4,6,9,10-tetrahydro-2,7-diazapyreniumdiiodide; 1,1',2,2'-tetramethyl-4,4'-bispyridinium; 1,1',2-trimethyl-4,4'-bispyridinium; N,N'-dimethyl-2,7-diazapyrenium; N-methyl-N'-(p-toloyl)-2,7-diazapyrenium, 1,1'-dimethyl-2-phenyl-6-(p-toloyl)-4,4'-bispyridium diperchlorate; 1,1'-dimethyl-2-phenyl-4,4'-bispyridium diperchlorate; 6-(phenyl)-1,1',2-trimethyl-4,4'-bispyridium diperchlorate; 6-(phenyl)-1,1',2-trimethyl-4,4'-bispyridium diperchlorate or 1,1'-dimethyl-2-phenyl-6-(2,5-dichloro-3-thienyl)-4,4'-bispyridiumdiperchlorate. (1) Xa, XbS, N or O; Ra, Rbalkyl, aryl, alkylaryl, alkenyl, halogen, CN, OCN, COOH, COOR1>, CONHR1>, NO2, OH, OR1>, NH2, NHR1>, NR'R, SH or SR1>; R'R : alkyl, aryl, alkylaryl, alkenyl or alkinyl or Ra and Rb together form a bridge between the two aromatic ring systems comprising 1-3 atoms of C, S, N or O bonded by single, double or triple bonds and optionally substituted by Re; RcR a and Rb; Y : CH2, O, S, NH, NR1>, COO, CONH, CHCH, CC or aryl; Aa, ZbCH3, -CHCH2, SH, -SS-, SiCl3, Si(OR)3, SiR(OR')(OR), SiR(OR')2, Si(R'R)NH2, Si(R'2)NH2, COOH, SO3, PO3H or NH2; n, q : 0-12; j, k : 0-6; p., m : 0-12.
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公开(公告)号:DE59610179D1
公开(公告)日:2003-04-03
申请号:DE59610179
申请日:1996-11-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor: LAUTERBACH CHRISTL , WEBER WERNER
IPC: H01L21/58 , H01L21/768 , H01L21/98 , H01L23/48 , H01L23/522 , H01L23/532 , H01L25/065 , H01L27/00
Abstract: PCT No. PCT/DE96/02108 Sec. 371 Date May 19, 1998 Sec. 102(e) Date May 19, 1998 PCT Filed Nov. 6, 1996 PCT Pub. No. WO97/19462 PCT Pub. Date May 29, 1997A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.
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公开(公告)号:DE59903868D1
公开(公告)日:2003-01-30
申请号:DE59903868
申请日:1999-09-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEBER WERNER , THEWES ROLAND , PLASA GUNTHER
IPC: G11C11/14 , G11C11/15 , G11C11/16 , H01F10/08 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
Abstract: The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.
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公开(公告)号:DE10056282A1
公开(公告)日:2002-05-23
申请号:DE10056282
申请日:2000-11-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KREUPL FRANZ , WEBER WERNER
Abstract: Artificial neuron (100) comprises a transistor (101) and a number of electrical contacts which can be contacted by the ends of nanostructures. A first connection (102) of the transistor is coupled to each end of the nanostructures. The nanostructures are preferably silicon nano-wires or carbon nano-tubes. The transistor is a MOSFET, a bipolar transistor or a MIFG transistor.
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公开(公告)号:DE10043440A1
公开(公告)日:2002-03-28
申请号:DE10043440
申请日:2000-09-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEBER WERNER , BERG HUGO VON DEN , THEWES ROLAND
Abstract: An impedance converter (1) has an input connected with an evaluation line. The output of the impedance converter is connected to the ends of the bit lines (4a,4b) and the word lines (5a,5b) via switching components (7a,7b,9a,9b). A terminating resistor (R1) branches off from the evaluation line. A voltage evaluator (2) has an input connected with the ends of the bit lines by the switching components (8a,8b,11) via the evaluation line. A read voltage source (U1) is connected with the word lines by the switching components (6a,6b,16). Independent claims are also included for the following: (a) a method for reading memory locations in a magnetoresistive memory; (b) and the use of an impedance converter for buffering a read voltage of a memory location.
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公开(公告)号:DE10038890A1
公开(公告)日:2002-03-14
申请号:DE10038890
申请日:2000-08-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor: LAUTERBACH CHRISTL , WEBER WERNER
IPC: G11B7/0065 , G11B7/13 , G11C13/04 , H01L27/144
Abstract: The detector (111) has several cells each of which comprises a photodiode and a selection transistor formed on a substrate. The cells are mutually separated by trenches filled with insulator. The source of the transistor is connected to cathode of photodiode, while its drain and gate are connected to bit and word lines. Independent claims are also included for the following: (a) Holographic storage element; (b) Detector manufacturing method
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公开(公告)号:DE59607894D1
公开(公告)日:2001-11-15
申请号:DE59607894
申请日:1996-11-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEBER WERNER , THEWES ROLAND
IPC: H01L21/8247 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
Abstract: The object of the application is a method of producing a neuron MOS transistor in which the necessary coupling capacitances are obtained either via capacitors with a similar structure to transistors or via transfer gates of a CMOS standard process arranged as capacitors. A substantial advantage is the great compatibility of the process with a standard CMOS process.
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公开(公告)号:DE102008062499B4
公开(公告)日:2013-05-16
申请号:DE102008062499
申请日:2008-12-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: RABERG WOLFGANG , SCHOEN FLORIAN , WEBER WERNER , WINKLER BERNHARD
Abstract: Verfahren zum Herstellen eines Mikroelektromechanisches-System-Bauelements (MEMS-Bauelements), wobei das Verfahren folgende Schritte umfasst: Bereitstellen eines Arbeitsstücks (102; 202), wobei das Arbeitsstück ein Substrat (104), eine auf dem Substrat (104) angeordnete vergrabene Oxidschicht (106, 206, 306, 406) und ein auf der vergrabenen Oxidschicht (106, 206, 306, 406) angeordnetes erstes halbleitendes Material (108, 208, 308, 408) aufweist, wobei das erste halbleitende Material (108, 208, 308, 408) eine obere Oberfläche aufweist; Bilden zumindest eines Grabens (110, 210, 310, 410) in dem ersten halbleitenden Material (108, 208, 308, 408), wobei eine obere Oberfläche der vergrabenen Oxidschicht (106, 206, 306, 406) an dem Boden des zumindest einen Grabens (110, 210, 310, 410) freigelegt wird, wobei der zumindest eine Graben (110, 210, 310, 410) eine erste Seitenwand und eine der ersten Seitenwand gegenüberliegende zweite Seitenwand aufweist; Bilden einer Isoliermaterialschicht (240; 115; 215; 315; 415; 515) auf der oberen Oberfläche des ersten halbleitenden Materials...
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50.
公开(公告)号:DE102005035383B4
公开(公告)日:2011-04-21
申请号:DE102005035383
申请日:2005-07-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEBER WERNER , GLASER RUPERT , SCHLIEP FRANK , STOEHR ANNELIE , LAUTERBACH CHRISTL , STURM THOMAS
IPC: G06F13/00 , G06F15/173 , G08B17/00
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