公开(公告)号：DE10318078A1

公开(公告)日：2004-11-25

申请号：DE10318078

申请日：2003-04-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO

IPC: H01L21/60 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/50 ,  H01L21/56

Abstract: Protecting the wiring on wafers/chips comprises covering the wafer (1) with the wiring on its whole surface with an organic layer (12) to protect the wiring from corrosion and oxidation and form a sealed coating of the metal surface of the wiring.

公开(公告)号：DE10241589A1

公开(公告)日：2004-03-25

申请号：DE10241589

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  UHLENDORF INGO ,  SCHENK ANDRE ,  WOLLANKE ALEXANDER

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/485

Abstract: Process for solder-stop structuring protrusions on wafers (3) such as three dimensional contact structures (1) in the form of elastic or flexible contact bumps comprises depositing a resist on the tip of the three dimensional structure, depositing a solder-stop layer over a metallization including the resist, and removing the resist on the tip of the three dimensional structure including the solder-stop layer covering it.

公开(公告)号：JP2004006772A

公开(公告)日：2004-01-08

申请号：JP2003093635

申请日：2003-03-31

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit having an improved fuse structure part and laser fuse links. SOLUTION: The fuse structure part in an integrated circuit chip comprises an insulated semiconductor substrate, a fuse bank 410 which is constituted of a plurality of the parallel fuse links 402, 404 and 404 on the same plane and which are integrated with the insulated semiconductor substrate and voids 410 and 412 which scatter between pairs of fuse links and which extend across the plane delimited by the fuse links on the same plane. The voids 410 and 412 surrounding a spot 420 to be hit by a laser beam during a fusing operation function as crack stops for preventing damage against an adjacent circuit element or the other existing fuse link. Thus, a denser pitch between fuses can be obtained by suitably forming and positioning the voids. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001068555A

公开(公告)日：2001-03-16

申请号：JP2000210177

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  GABRIEL DANIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To combine a laser actuation fuse with an electric starting fuse in order to increase total yield of product. SOLUTION: A plurality of different types of fuses 510, each serving a specified purpose, are arranged on a semiconductor integrated circuit wafer, such that a type of fuse can be actuated without missing the function of different types of fuses. A first type of fuse, e.g. a laser actuation fuse, is principally used for repairing a wafer level defect and a second type of fuse, e.g. an electric starting fuse, is used for repairing a defect found after an IC chip is mounted on a module and a stress is applied to the module during burn-in test. The module level defect is an unit cell trouble corrected normally by an electrically programmed fuse, in order to actuate a module level redundancy arrangement.

公开(公告)号：WO0163648A3

公开(公告)日：2002-04-18

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定用于期望的电熔丝的图案，其中该图案包括除了熔丝部分的局部变窄的区域之外基本恒定宽度的熔丝部分 在此电熔丝被设计为吹塑。 该方法然后包括提供光刻掩模衬底并且在光刻掩模衬底上产生适于吸收能量束的透射的熔丝掩模元件。 熔丝掩模元件具有基本恒定宽度的第一掩模部分和与熔丝部分的局部缩窄区域对应的第二掩模部分，第一掩模部分对应于基本恒定宽度的期望电熔丝图案部分。 第二掩模部分包括与第一掩模部分隔开的另外的掩模元件，变窄的宽度部分或第一掩模部分中的间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的配置，该电图案包括保险丝部分的局部变窄的区域，在电熔丝被设计成在该区域处被吹过，在通过能量束通过光刻掩模并且到 抗蚀剂层。 优选地，在所确定的熔丝图案上具有基本恒定宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：JP2000353750A

公开(公告)日：2000-12-19

申请号：JP2000144824

申请日：2000-05-17

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIRIHATA TOSHIAKI ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/82 ,  H01H85/00 ,  H01L23/525 ,  H01H85/044

Abstract: PROBLEM TO BE SOLVED: To array a larger number of fuses densely by electrically connecting at least two fuses that contain a fusing part arrayed in a first level of a multi- layer semiconductor device, respectively. SOLUTION: Each fuse 13 contains a part 15 that is actually fused. The part 15 to be fused is arrayed in a first metal level M1. Like the other part of the fuse 13, the part 15 that is actually fused is made typically of a electrically conductive material, especially aluminum. A termination of each part 15 to be fused is connected to a connector bias 17 that connects that fuse 13 with a connector 19. A gate contact 23 is vertical to a direction of the fuse 13. The gate contact 23 can be connected to a ground that is common to all of existing fuse circuits. Therefore, fuse density is doubled without narrowing the fuse pitch.

公开(公告)号：JP2000323578A

公开(公告)日：2000-11-24

申请号：JP37247499

申请日：1999-12-28

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108 ,  H01H85/046

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit which has a improved fuse structure and a laser fuse link. SOLUTION: A fuse structure within an integrated circuit chi is described which includes an insulated semiconductor substrate, a fuse band 4 consisting of a plurality of parallel fuse links 402, 404, and 406 on the same plane and united with the insulated semiconductor substrate, and voids 410 and 412 scattered among fuse links each in a pair and extending beyond the plane demarcated by the fuse links on the same plane. The voids 410 and 412, surrounding the spot 420 which should be hit with a laser beam during the operation of fuse fusion function as crack stopper for preventing damages to the adjacent circuit element or other existing fuse link. Closer pitch between fuses can be obtained by forming and positioning the voids properly.

公开(公告)号：JP2000252364A

公开(公告)日：2000-09-14

申请号：JP2000047093

申请日：2000-02-24

Applicant: IBM ,  SIEMENS AG

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  KAARU JIEI RADENSU

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a fuse link structure which reduces the magnitude of damage which is caused when a fuse element is blown and to provide its method. SOLUTION: This integrated circuit is provided with a main element 102. The integrated circuit is provided with a redundant element 104 which is replaced selectively with the main element 102 by at lease one fuse. The fuse contains a first layer 401 which comprises at least one fuse link region 402, contains a second layer 401 on the first layer, a gap 410 inside the second layer on the fuse link region 402, and contains a fuse window 408 in a dielectric layer 407. Since the gap 410 guides energy and a fuse material to the fuse window 408 from the fuse link region 402, it is possible to reduce damage to a circumferential structure.

公开(公告)号：JP2000091438A

公开(公告)日：2000-03-31

申请号：JP23860699

申请日：1999-08-25

Applicant: SIEMENS AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  EINSPRUCH FRED

IPC: H01L21/82 ,  G11C29/04 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/00 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To enable electrical fusion at the voltage of a specific value by connecting a fuse link at its one end with an individual connector terminal having a sectional region larger than its sectional region, and by connecting the fuse link at its other end with a common connector terminal having a sectional region which is larger than that of the sectional region of the individual connector terminal. SOLUTION: A semiconductor device 40 includes a board 41, on whose surface there is provided a redundant operating wiring, including many fuse-links 44 or a fuse bank used as a severe pitch array 42 for custom wirings. The fuse link 44 is connected at its one end with an individual connector terminal 43, having a sectional region about twice as large as its sectional region to be connected at its other end, with a common connector terminal 45 having a sectional region about twice as large as that of the individual connector terminal 43. As a result, heating caused by the maximized resistance difference between the fuse link 44 and the common connector terminal 45 is promoted to make possible electrical fusion at a voltage of about 10 V.

公开(公告)号：WO0199148A3

公开(公告)日：2002-08-29

申请号：PCT/US0119240

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： IYER SUNDAR K ,  BRINTZINGER AXEL ,  SMEYS PETER ,  NARAYAN CHANDRASEKHAR ,  IYER SUBRAMANIAN

IPC: H01L23/525 ,  H01L27/102

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode (104) including a first dopant type, and an anode (102) including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link (106) connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction (111) therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer (103) is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Abstract translation: 根据本发明的用于半导体器件的熔断器包括包括第一掺杂剂型的阴极（104）和包括第二掺杂剂类型的阳极（102），其中第二掺杂剂类型与第一掺杂剂类型相反。 熔丝连接（106）连接阴极和阳极并且包括第二掺杂剂类型。 熔丝链和阴极在其间形成结（111），并且该结被配置为相对于阴极电位和阳极电位被反向偏置。 在结上形成导电层（103），使得在结处流动的电流被转移到导电层中以增强材料迁移以对熔丝进行编程。