公开(公告)号：JPH10256551A

公开(公告)日：1998-09-25

申请号：JP3989398

申请日：1998-02-23

Applicant: IBM

Inventor： DONALD C WHEELER ,  JEFFLE P GANVINO ,  LEWIS L TSU ,  MANDELMAN JACK A ,  REBECCA D MI

IPC: H01L21/027 ,  H01L21/266 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a new FET (asymmetrical field effect transistor) with improved reliability and performance. SOLUTION: An asymmetrical field effect transistor includes a first region 54 to be a source, a second region 53 to be a drain, a thin gate oxide 52 and a gate electrode 51. The gate electrode is asymmetrical and one of its side wall is sloped. The second region 53 extends under the sloped side wall 56. The part of the second region 53 extending under the gate electrode 51 is doped more lightly than the rest of the second region 53. The second region 53 is further provided with a sloped junction edge 58 under the gate electrode 51.

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004128494A

公开(公告)日：2004-04-22

申请号：JP2003325279

申请日：2003-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BYONJU PAKU ,  MANDELMAN JACK A ,  FURUKAWA TOSHIHARU

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

Abstract: PROBLEM TO BE SOLVED: To provide a multi-mesa FET structure having a doped sidewall for a source/drain region and its forming method. SOLUTION: This method makes use of the fact that when using a doping method which does not depend on a geometric shape such as a vapor doping or a plasma doping, a uniform doping of the whole sidewall is obtained by exposing the source and the drain sidewall during manufacturing. As a result, a device manufactured can have a large quantity of current per unit area of a silicon because it has a threshold voltage and a current density that does not depend on the depth and controlled with accuracy, and also its mesa quantity is extremely high compared with a mesa which can be formed by a conventional technology. Instead of a normal subtractive etching method, a multi-mesa FET structure forming method using a Damascene method gate process or a Damascene method alternate gate process is included. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004040095A

公开(公告)日：2004-02-05

申请号：JP2003178790

申请日：2003-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  YANG HAINING

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM array employing a small vertical transistor of bitline capacitance. SOLUTION: A DRAM array comprising DRAM cells employing the vertical transistor increases electrical reliability and reduces the bitline capacitance by the use of an asymmetric structure in connection between a wordline 310 and the transistor. Thereby, the DRAM array permits the use of wider connection between the wordline 310 and a transistor electrode. Also, the word line 310 is used as an etch stop to protect a transistor gate 205 during the patterning of the wordline 310. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003273235A

公开(公告)日：2003-09-26

申请号：JP2003053740

申请日：2003-02-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MANDELMAN JACK A ,  FILIPPI RONALD G ,  JEFFREY P GANBINO ,  RICHARD A WAKNICK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L21/76897 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with interconnected conductor lines.
SOLUTION: The semiconductor device includes a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines surrounded by an insulator formed on the lower ILD layer are formed on the top surface of the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and the set is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on an upper level. Each of the upper conductor lines has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供配备有互连的导线的半导体器件。 解决方案：半导体器件包括具有形成在衬底上的顶表面的下层间介电层（ILD）层。 在下部ILD层的上表面形成有由下部ILD层形成的绝缘体围绕的多个下部导体线。 一组电阻螺柱中的每一个具有侧壁，下端和上端，并且该组在下端处连接到下导体线的顶部。 在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。 上导线形成在上层。 每个上导体线具有与相应的一个电阻螺柱接触的底表面。 中间ILD层覆盖中间导体，用于将中间导体线与上导体线电绝缘和分离。 版权所有（C）2003，JPO

公开(公告)号：JP2002134631A

公开(公告)日：2002-05-10

申请号：JP2001300150

申请日：2001-09-28

Applicant: IBM

Inventor： ADKISSON JAMES W ,  RAMACHANDORA DEIVAKARUNI ,  JEFFREY P GANBINO ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that comprises an embedded DRAM device and a logic device, and to provide a its manufacturing method. SOLUTION: This device comprises a monocrystal substrate having an almost flat surface, a first surface region on the flat surface having a silicon on insulator region, a second surface region on the flat surface which is a monocrystal bulk region, an embeded logic device which is formed in the silicon on insulator region, an embedded memory device which is formed in the monocrystal bulk region, and a trench in the bulk monocrystal region.

公开(公告)号：JP2000232210A

公开(公告)日：2000-08-22

申请号：JP2000017633

申请日：2000-01-26

Applicant: IBM

Inventor： LEWIS L SUU ,  DAVID E KOTEKKI ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor which is annealed before formation of a bit line and formed on an active region for the purpose of reducing the size of a memory cell. SOLUTION: This integrated circuit structure is provided with at least a transistor structure, a ferroelectric capacitor 5 of transistor structure, and a conductive circuit 70 located between the transistor structure and the ferroelectric capacitor 50. The ferroelectric capacitor 50 is annealed before the conductive contact 70 is formed.

公开(公告)号：JP2000040756A

公开(公告)日：2000-02-08

申请号：JP16743599

申请日：1999-06-14

Applicant: IBM

Inventor： LEWIS L SUU ,  MANDELMAN JACK A

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To design and manufacture a high density flash memory by few number of treatment processes by a method, wherein a polycrystalline silicon spacer is formed on the second side wall having the tilt angle larger than the first sidewall, in such a manner that one side of the polycrystalline silicon spacer is opposed to a word line. SOLUTION: A gate oxide film 3 is formed on a substrate 1, and a gate 4, consisting of n+ or p+ dopant doped polycrystalline silicon, is formed. Then, one sidewall (a second sidewall) 4B of the gate 4 is formed vertically, and the other sidewall (a first side wall) 4A is formed at a tilt angle 45 to 65 degrees. Then, a polycrystalline silicon layer is adhered over the entire surface of a nitride layer and an oxide layer, and the first spacer of polycrystalline silicon and the second spacer which is connected to the first spacer are formed on the part, adjacent to the second sidewall 4B by anisotropic etching in the direction vertical to the surface of the silicon substrate 1. The first and the second spacers are incorporated and function as a sidewall floating gate 7.

公开(公告)号：JPH11265574A

公开(公告)日：1999-09-28

申请号：JP37452498

申请日：1998-12-28

Applicant: SIEMENS AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  KLEINHENZ RICHARD L ,  MANDELMAN JACK A

IPC: G11C11/408 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4074

Abstract: PROBLEM TO BE SOLVED: To make a standby operation mode in which a leakage current is reduced executable by obtaining whether a DRAM is in the standby operation mode or in a normal operation mode and turning a first power source with respect to the array of the DRAM off when the DRAM is in the standby operation mode and maintaing the first power source with respect to the array of the DRAM when it is in the normal operation mode. SOLUTION: A collar 268 is provided at the upward part of a trench in order to separate a p-well from a storage node, an n-well area or an n-band area exists at the downward direction of the p-weel and the embedding plate 265 of capacitances in these n areas is connected to the embedding plates of other DRAM cells of the array. The reducing of stand-by currents is achieved by switching off a voltage generator or a voltage pump supplying a proper voltage to the n-well during the stanby mode and the voltage pump for the n-band with respect to the array of the DRAM is kept as switched on.

公开(公告)号：JPH11168190A

公开(公告)日：1999-06-22

申请号：JP27728998

申请日：1998-09-30

Applicant: SIEMENS AG ,  IBM

Inventor： MANDELMAN JACK A ,  HSU LOUIS L C ,  ALSMEIER JOHANN ,  TONTI WILLIAM R

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a small trench capacitor having sufficiently low parasitic leakage. SOLUTION: A transistor, which includes a gate and first and second diffused regions are provided. A trench capacitor in a substrate electrically connects a dielectric color part 168 at the upper-side part of a trench, a diffused region embedded in a substrate surrounding the lower part of the trench capacitor, a transitor and the capacitor. A node diffused region is included on a collar part. A third diffused region 269 is provided in a substrate neighboring the color part. In order to decrease the leakage, an adequate concentration of doping agent for enhancing the threshold voltage of the gate of a parasitic transistor, which is formed of the color part, the embedded diffused region and node diffusion, is provided.