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公开(公告)号：CA2723046C
公开(公告)日：2013-02-19
申请号：CA2723046
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC: H03G1/00 , H04B1/16 , H03G3/00 , H03G3/20 , H03G3/30 , H04B1/30 , H04J13/00 , H04L27/22 , H04L27/38
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：CA2438333C
公开(公告)日：2011-11-01
申请号：CA2438333
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT CHRISTOPHER
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：SG155232A1
公开(公告)日：2009-09-30
申请号：SG2009055369
申请日：2005-05-20
Applicant: QUALCOMM INC
Inventor： HANSQUINE DAVID W , WALKER BRETT C , MUNEER MUHAMMAD ASIM
IPC: H04L12/40 , H04L12/413
Abstract: Embodiments disclosed herein address the need for a single wire bus interface, which will allow the reduction of connectors for devices (220, 230). A device (220) communicates with a second device (230) via a single wire bus using a driver (1120) for driving the bus with a write frame (910) comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame (920). In yet another aspect, a device (230) communicates with a second device (220) via a single wire bus using a receiver (1320) for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver (1320) for driving return read data associated with the address when the write indicator identifies a write frame. Further modifications are disclosed, which also apply a Single-Wire Serial Bus Interface (SSBI) protocol.
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公开(公告)号：DE60036887T2
公开(公告)日：2008-07-24
申请号：DE60036887
申请日：2000-11-03
Applicant: QUALCOMM INC
Inventor： GARD KEVIN G , SAHOTA KAMAL GURKANWAL , WALKER BRETT C
Abstract: A device for use in a wireless communications system that reduces the amount of phase noise in the carrier signals due to powering down circuit elements for reducing power consumption. The device includes one or more carrier signal generators coupled to a transmitter. Each signal generator provides a respective carrier signal. The transmitter receives and modulates one or more carrier signals with one or more input signals to generate a modulated signal, which is gated on and off during a discontinnous data transmission. The transmitter includes one or more input buffers, with each input buffer receiving and buffering a respective carrier signal. The input buffers are maintained biased for the duration of the data transmission, even as the modulated signal is gated on and off, to provide a constant load for the signal generators and to isolate the carrier signal generators from switching noise. Some other active elements in the transmitter may be powered down when the modulated signal is gated off to further reduce power consumption.
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公开(公告)号：BRPI0511276A
公开(公告)日：2007-12-04
申请号：BRPI0511276
申请日：2005-05-20
Applicant: QUALCOMM INC
Inventor： HANSQUINE DAVID W , WALKER BRETT C , MUNEER MUHAMMAD ASIM
IPC: H04L12/10 , H04L12/40 , H04L12/413
Abstract: Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.
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Patent Agency Ranking
公开(公告)号：AU2007224396A1
公开(公告)日：2007-11-01
申请号：AU2007224396
申请日：2007-10-15
Applicant: QUALCOMM INC
Inventor： KANG INJUP , HOLENSTEIN CHRISTIAN , CHALLA RAGHU , WALKER BRETT C , SIH GILBERT C , LI TAO , SEVERSON MATTHEW L , RAGHUPATHY ARUN , PETERZELL PAUL E
Abstract: An apparatus and method in a wireless communication system, the apparatus comprising: first means for amplifying a received signal; means for cancelling a DC offset in the amplified signal; second means for digitally amplifying the DC offset cancelled signal; and means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.
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公开(公告)号：BR0114908A
公开(公告)日：2006-05-09
申请号：BR0114908
申请日：2001-10-24
Applicant: QUALCOMM INC
Inventor： SEE PUAY HOE , PETERZELL PAUL E , WALKER BRETT C
Abstract: A zero Intermediate Frequency (IF) transmitter and receiver are implemented within a transceiver to eliminate interference in the receive band. An output of a tunable high oscillator to generate a frequency source that is an integer multiple of the desired transmit LO frequency. The frequency source is coupled to an amplitude limiter and frequency divider. The output of the frequency divider is used as the transmit LO to directly upconvert baseband signals to the desired output frequency without the need for an IF stage. Direct upconversion of the baseband transmit signals without an IF stage eliminates spurious frequency products that are produced in the receive band.
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公开(公告)号：AU2003290822A8
公开(公告)日：2004-06-03
申请号：AU2003290822
申请日：2003-11-12
Applicant: QUALCOMM INC
Inventor： BARNETT KENNETH , WALKER BRETT C , GARD KEVIN
Abstract: A radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control is provided. The RF driver amplifier system comprises a linear transconductor receiving an input voltage and providing a controlled current based on input voltage received, temperature compensation circuitry for varying current from the linear transconductor according to absolute temperature, an exponential current controller receiving current varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry, thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry. Control current passes from the inductive degeneration compensator to the driver amplifier circuitry. Output gain from the driver amplifier circuitry varies linearly in decibels with respect to the input voltage.
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公开(公告)号：AU2003209016A8
公开(公告)日：2003-09-02
申请号：AU2003209016
申请日：2003-02-04
Applicant: QUALCOMM INC
Inventor： WALKER BRETT C , MOLLENKOPF STEVEN M , SEE ANDREW
Abstract: A transmitter (108) converts a digital baseband signal input (150) for transmission by an antenna (114) to support multiple communication standards. An over-deviation phase multiplier (130) increases signal phase deviation by a factor of M. A digital phase modulator (176) applies trigonometric lookup tables. A digital intermediate frequency up-converter (132) up-shifts frequencies of desired signal content. First and second digital-to-analog converters (DACs) (134) and (136) use relatively low-bit operations, which add DAC noise (212). First and second low pass filters (138) and (140) apply rejection above frequencies of desired signal content. An analog I/Q modulator (142) converts from complex to real signals, adding an unwanted signal spaced from the desired signal content by an intermediate frequency multiple. A limiter (144) reduces amplitude modulated noise. An over-deviation phase divider (146) divides signal phase deviation by 1/M to reduce phase modulated noise.
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公开(公告)号：CA2723046A1
公开(公告)日：2002-08-29
申请号：CA2723046
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC: H03G1/00 , H04B1/16 , H03G3/00 , H03G3/20 , H03G3/30 , H04B1/30 , H04J13/00 , H04L27/22 , H04L27/38
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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