GENERADOR DE SECUENCIAS DE RUIDO PSEUDOALEATORIO DE ROTACION RAPIDA.

    公开(公告)号:ES2241357T3

    公开(公告)日:2005-10-16

    申请号:ES99965016

    申请日:1999-11-18

    Applicant: QUALCOMM INC

    Abstract: Generador de secuencias de ruido pseudoaleatorio (PN) de rotación rápida que comprende: - un registro de desplazamiento con retroalimentación lineal LFSR (520) para generar estados PN; - un contador de índices (530) para proporcionar un índice de estados de dicho LFSR; y - una unidad de control de rotación controlable (540) para ajustar la frecuencia de cambio de estado en dicho LFSR (520) y, de forma paralela, en dicho contador de índices (530); caracterizado porque - dicho registro de desplazamiento con retroalimentación lineal LFSR (520) y dicho contador de índices (530) son cargables y porque el generador de secuencias de ruido pseudoaleatorio (PN) de rotación rápida comprende además - un procesador de señales digitales DSP (500); - un contador de referencia (510) para proporcionar un estado de referencia a dicho procesador de señales digitales DSP (500); - una tabla de estados para almacenar un subgrupo de estados PN y sus correspondientes valores de índice, que puede ser recuperadapor dicho DSP.

    43.
    发明专利
    未知

    公开(公告)号:DE69924867D1

    公开(公告)日:2005-05-25

    申请号:DE69924867

    申请日:1999-11-18

    Applicant: QUALCOMM INC

    Abstract: A novel and improved method and apparatus for a fast-slewing pseudorandom noise sequence generator is described. One or more loadable PN generators are controlled by a DSP or microprocessor in conjunction with a free-running counter which maintains a reference offset count. The PN generator will typically be part of a finger or searcher. The DSP or microprocessor may assist in other finger or searcher functions as well as the slew function, and can control one or more fingers and/or searchers. Each PN generator is comprised of a loadable linear feedback shift register (LFSR) or its equivalent, a loadable counter for maintaining an index of the state of that particular PN generator, and a slew control device capable of receiving a slew command and controlling the LFSR and index counter to enact an advance or a retard of a certain offset distance.

    44.
    发明专利
    未知

    公开(公告)号:AT293807T

    公开(公告)日:2005-05-15

    申请号:AT99965016

    申请日:1999-11-18

    Applicant: QUALCOMM INC

    Abstract: A novel and improved method and apparatus for a fast-slewing pseudorandom noise sequence generator is described. One or more loadable PN generators are controlled by a DSP or microprocessor in conjunction with a free-running counter which maintains a reference offset count. The PN generator will typically be part of a finger or searcher. The DSP or microprocessor may assist in other finger or searcher functions as well as the slew function, and can control one or more fingers and/or searchers. Each PN generator is comprised of a loadable linear feedback shift register (LFSR) or its equivalent, a loadable counter for maintaining an index of the state of that particular PN generator, and a slew control device capable of receiving a slew command and controlling the LFSR and index counter to enact an advance or a retard of a certain offset distance.

    Programmable matched filter searcher

    公开(公告)号:HK1044239A1

    公开(公告)日:2002-10-11

    申请号:HK02105822

    申请日:2002-08-09

    Applicant: QUALCOMM INC

    Abstract: A novel and improved method and apparatus for searching is described. Channel data is despread utilizing a matched filter structure. The in-phase and quadrature amplitudes of the despreading delivered to coherent accumulators to sum for a programmable duration of time. The amplitude accumulations are squared and summed to produce an energy measurement. The energy measurement is accumulated for a second programmable time to perform non-coherent accumulation. The resulting value is used to determine the likelihood of a pilot signal at that offset. Each matched filter structure comprises an N-value shift register for receiving data, a programmable bank of taps to perform despreading and optional Walsh decovering, and an adder structure to sum the resulting filter tap calculations.

    Mixed analog and digital integrated circuits

    公开(公告)号:AU2002238123A1

    公开(公告)日:2002-09-19

    申请号:AU2002238123

    申请日:2002-02-22

    Applicant: QUALCOMM INC

    Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

    47.
    发明专利
    未知

    公开(公告)号:BR9913552A

    公开(公告)日:2001-10-09

    申请号:BR9913552

    申请日:1999-09-03

    Applicant: QUALCOMM INC

    Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method of performing position location in a wireless subscriber unit having a local oscillator, including the steps of receiving a position location request, acquiring a timing signal when a sufficient period of time has elapsed since the local oscillator has been corrected and correcting said local oscillator using a correction signal based on said timing signal, substantially freezing the correction signal, performing a position location procedure using the local oscillator with the correction signal applied, and ending said position location procedure.

    48.
    发明专利
    未知

    公开(公告)号:BR9913550A

    公开(公告)日:2001-10-09

    申请号:BR9913550

    申请日:1999-09-03

    Applicant: QUALCOMM INC

    Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment comprises a method for performing position location using a set of signals transmitted from a set of satellites including the steps of storing coarse search data, performing a coarse search on said coarse search data for each satellite from said set of satellites, receiving fine search data, performing a set of fine searches on said fine search data, each fine search being performed on a different time segment of said fine search data, and reporting results.

    49.
    发明专利
    未知

    公开(公告)号:ID29480A

    公开(公告)日:2001-08-30

    申请号:ID20010799

    申请日:1999-09-03

    Applicant: QUALCOMM INC

    Abstract: A mobile device (10) comprises a receiver and a coherent integrator (104), wherein the receiver is configured to receive a first signal from a satellite, the first signal including a navigation message. The coherent integrator is configured to coherently integrate first signal samples for a particular coherent integration interval. When the coherent integration interval straddles a data boundary of the navigation message, the coherent integration is divided into a section before the data boundary of the navigation message and a section after the data boundary of the navigation message

    Generalized address generation for bit reversed random interleaving

    公开(公告)号:AU4059000A

    公开(公告)日:2000-10-16

    申请号:AU4059000

    申请日:2000-03-30

    Applicant: QUALCOMM INC

    Abstract: A novel and improved method and apparatus for address generation in an interleaver is provided. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. The bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. The second bit reversed address fragment is selected when the first bit reversed address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.

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