Abstract:
An integrated circuit device includes a first substrate supporting a pair of conductive interconnects, for example pillars. The device also includes a second substrate on the pair of conductive interconnects. The pair of conductive interconnects is arranged to operate as a first 3D solenoid inductor. The device further includes a conductive trace coupling the pair of conductive interconnects to each other.
Abstract:
An inductor is provided on a substrate that includes a capacitor. The inductor comprises a series of wire loops. An end of the wire loop is wire bonded to the capacitor.
Abstract:
A resonator (300) includes a piezoelectric core (132), a set of electrodes (104, 106, 304, 306), and at least one ground terminal (108, 308). The electrodes are arranged on the piezoelectric core (132) and also includes at least one input electrode (104, 304) having a first width and at least one output electrode having a second width (106, 306) that differs from the first width. The ground terminal (108, 308) is also on the piezoelectric core (132).
Abstract:
An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.
Abstract:
An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross sectional shape than the second via.
Abstract:
A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
Abstract:
A method for metal semiconductor wafer bonding for high-Q capacitors or varactors is provided. An exemplary capacitor (210) includes a first plate (310) formed on a glass substrate (305), a second plate (330), and a dielectric layer (315). No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer (325) that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer comprising an alloy of the materials of the first plate and the dielectric layer is thermo compression bonded to the first plate and the dielectric layer.
Abstract:
A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.
Abstract:
A package (300) includes a redistribution portion (302), a first portion (204), and a second portion (206). The first portion is coupled to the redistribution portion. The first portion includes a first switch (241) comprising a plurality of switch interconnects (245), and a first encapsulation layer (240) that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters (261). Each filter includes a plurality of filter interconnects (265). The second portion also includes a second encapsulation layer (260) that at least partially encapsulates the first plurality of filters. The first portion includes a second switch (243) positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters (263) positioned next to the first plurality of filters, where the second encapsulation layer at least partially encapsulates the second plurality of filters.
Abstract:
In an illustrative example, an apparatus (100) includes a passive-on-glass (POG) device (104) integrated within a glass substrate (102). The apparatus further includes a semiconductor die (106) integrated within the glass substrate.