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    42.
    发明专利
    未知

    公开(公告)号：ITMI991017A1

    公开(公告)日：2000-11-11

    申请号：ITMI991017

    申请日：1999-05-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C11/56 ,  G11C16/34

    Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

    43.
    发明专利
    未知

    公开(公告)号：IT1303201B1

    公开(公告)日：2000-10-30

    申请号：ITTO980990

    申请日：1998-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C16/12

    Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

    44.
    发明专利
    未知

    公开(公告)号：ITMI20001804D0

    公开(公告)日：2000-08-02

    申请号：ITMI20001804

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PIERLUIGI ,  PASOTTI MARCO ,  GUATINI GIOVANNI

    IPC: G06F1/26

    Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.

    45.
    发明专利
    未知

    公开(公告)号：ITMI20000832D0

    公开(公告)日：2000-04-13

    申请号：ITMI20000832

    申请日：2000-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI ,  ROCCHI ALESSANDRO ,  BISIO MARCO ,  DE SANDRE GUIDO ,  PASOTTI MARCO

    IPC: G01R31/28

    Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

    46.
    发明专利
    未知

    公开(公告)号：ITTO990944D0

    公开(公告)日：1999-10-29

    申请号：ITTO990944

    申请日：1999-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C11/56 ,  G11C16/28

    Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

    50.
    发明专利
    未知

    公开(公告)号：DE60317457D1

    公开(公告)日：2007-12-27

    申请号：DE60317457

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  BORGATTI MICHELE ,  ROLANDI PIER LUIGI

    IPC: G11C5/14 ,  G06F12/00 ,  G11C16/30

    Abstract: The present invention relates to a 8Mb application-specific embeddable flash memory. It comprises three content-specific I/O ports and delivers a peak read throughput of 1.2GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1 Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18 mu m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 mu m .

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