-
公开(公告)号：FR2902928B1
公开(公告)日：2008-10-24
申请号：FR0605645
申请日：2006-06-23
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER
Abstract: The method involves controlling a value of a drain current (ID) delivered by an output electrode of a transistor (TR) by adjusting a value of a polarization voltage (V-BS) of a silicon on insulator (SOI) type polarizable semiconductor case, where the transistor is placed in the case. The value of the polarization voltage is adjusted based on a value of a control signal (SC) using an inverter limiter (INV). An independent claim is also included for an integrated circuit comprising a transistor.
-
公开(公告)号：DE60315612D1
公开(公告)日：2007-09-27
申请号：DE60315612
申请日：2003-02-14
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER , PERSECHINI PASCAL
Abstract: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.
-
公开(公告)号：FR2875972B1
公开(公告)日：2006-12-15
申请号：FR0410367
申请日：2004-09-30
Applicant: ST MICROELECTRONICS SA
Inventor： OUSTALOUP ALAIN YVES , DEVAL YANN , BELOT DIDIER , MELCHIOR PIERRE , BEGUERET JEAN BAPTISTE , BADETS FRANCK , LAGARESTE VINCENT
Abstract: The synthesizer has a phase locked loop (PLL) with a variable frequency divider (45) converting an output signal from a VCO to a suitable frequency for comparison with a reference in a PFD. A lowpass filter (43) of fractional order feeds a control voltage from a charge pump to the VCO according to the measured phase difference between the divided VCO signal and the reference frequency signal. The lowpass loop filter is preferably made up of a first stage (431) of integer order and a second stage (432) of order between zero and one, especially 0.5.
-
公开(公告)号：DE60122629D1
公开(公告)日：2006-10-12
申请号：DE60122629
申请日：2001-06-27
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER
Abstract: The amplifier device of differential structure comprises an input stage with transistors (T1A,T1B), an output stage with transistors (T2A,T2B) connected in cascade with the input stage, and a load stage comprising several elementary circuits (CEAi,CEBi), where i is from 1 to n, each containing a capacitive lement (Ci) and an inductive element (Li) with the Q-factor greater than 10, and distinct resonant frequencies. All curves of elementary gain associated with two elementary circuits having the resonant frequencies immediately neighbouring overlap this side of 3 dB threshold, within a tolerance, below the maximum gain value. The absolute value of tolerance is about 1 dB. The elementary circuits (CEAi,CEBi) are connected in series with the output stage, and the elementary circuits have at the resonant frequencies the same first value of impedance, within a tolerance, and the two elementary circuits with neighbouring resonant frequencies have at the median frequency the same second value of impedance, which is equal, within a tolerance, to half of the first value of impedance. The tolerance is equal to 20%. Each elementary circuit comprises a capacitive element (Ci) and an inductive element (Li) connected in parallel, and all inductive elements are identical. A receiver of radio-frequency signals comprises an amplifier device of the proposed type.
-
公开(公告)号：FR2871000B1
公开(公告)日：2006-08-11
申请号：FR0405636
申请日：2004-05-25
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER , LE GUASCOZ VINCENT , PACHE DENIS , BERLAND CORINNE , BERCHER JEAN FRANCOIS , HIBON ISABELLE , VILLEGAS MARTINE
Abstract: A signal modulation device comprises a delta-sigma modulator disposed for transforming an amplitude-modulation signal in baseband into a pulse signal. It also comprises a phase modulator receiving, at its input, analogue phase-modulation signals in baseband. The pulse signal is mixed with carrier signals upstream of the phase modulator. The modulation device is designed to form an input stage of a transmitter.
-
Patent Agency Ranking
公开(公告)号：FR2864727A1
公开(公告)日：2005-07-01
申请号：FR0403490
申请日：2004-04-02
Applicant: ST MICROELECTRONICS SA
Inventor： RAZAFIMANDIMBY STEPHANE , BELOT DIDIER , CARPENTIER JEAN FRANCOIS , CATHELIN ANDREA
Abstract: The component has a bulk acoustic wave resonator with a resonance frequency and an anti-resonance frequency. An inductor cancels the anti-resonance frequency of the resonator and has one Q-factor in a predetermined frequency range and another value of Q outside the frequency range. A capacitor adjusts the tuning of the resonator on the resonance frequency.
-
公开(公告)号：DE69821861T2
公开(公告)日：2004-12-30
申请号：DE69821861
申请日：1998-10-20
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER
Abstract: The quality factor for the two sets of inductance capacitance circuits is different, allowing the two circuits to be paralleled or for one of the circuits to be placed in the frequency stop band.
-
公开(公告)号：FR2836306B1
公开(公告)日：2004-07-16
申请号：FR0201939
申请日：2002-02-15
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER , PERSECHINI PASCAL
Abstract: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.
-
公开(公告)号：FR2841406A1
公开(公告)日：2003-12-26
申请号：FR0207856
申请日：2002-06-25
Applicant: ST MICROELECTRONICS SA
Inventor： BADETS FRANCK , BELOT DIDIER
-
公开(公告)号：FR2836306A1
公开(公告)日：2003-08-22
申请号：FR0201939
申请日：2002-02-15
Applicant: ST MICROELECTRONICS SA
Inventor： BELOT DIDIER , PERSECHINI PASCAL
Abstract: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.
-
-
-
-
-
-
-
-
-
Search Results
98
records
(took 0.022 seconds)
