公开(公告)号：DE60301119D1

公开(公告)日：2005-09-01

申请号：DE60301119

申请日：2003-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

IPC: G11C14/00 ,  G11C17/14

Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

公开(公告)号：FR2855902B1

公开(公告)日：2005-08-26

申请号：FR0306751

申请日：2003-06-04

Applicant: ST MICROELECTRONICS SA

Inventor： GENEVAUX FRANCK ,  JACQUET FRANCOIS

IPC: G11C7/06 ,  G11C7/12

Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.

公开(公告)号：FR2840445B1

公开(公告)日：2004-09-10

申请号：FR0206794

申请日：2002-06-03

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  SCHOELLKOPF JEAN PIERRE

IPC: G06F11/10 ,  G11C29/00 ,  H04L1/22

Abstract: The memory circuit equipped with a system for error correction comprises an address (ADD) bus (102), an input data (DIN) bus (108), an output data (Dout) bus (115), a memory store (100) with an address bus (113), an input data (DinSP) bus (114), and an output data (DoutSP) bus (110), and a circuit for error correction comprising an encoder (107). The memory circuit also comprises an address register (104) connected to the address bus (102) and storing the addresses corresponding only to the write operations in the memory, a data register (105) connected to the input data bus (108) for storing the data transmitted to the encoder (107), and a multiplexer (103) allowing to introduce a shift of a cycle in the write operation without modifying the read operation, in a manner to permit a longer computing time for the encoder. The memory store (100) is RAM with single port (SP) and comprises an internal address register (101) and an internal data register (106). The multiplexer (103) comprises two inputs, one connected to the address bus (102) and the other to the output of the address register (104), a single output connected to the address bus (102) and the other to the output of the address register (104), a single output connected to the address bus (113) of the memory store (100), and a control input for a Write Enable Negative (WEN) signal, that is for authorizing the write operation. The memory circuit also comprises a comparator (109) with two inputs, one connected to the address bus (102) and the other to the output of the address register (104), and a single output (112) connected to the control input of the second multiplexer (111) with two inputs, one connected to the output of the data register (105) and the other to the output data bus (110) of the memory store (100), and a single output connected to the output data bus (115). The memory circuit (claimed) is in three embodiments. In the second embodiment, the memory circuit comprises an additional memory store which is double-port, and an ECC decoder. In the third embodiment, the memory circuit comprises a synchronous static memory store which is single-port, and an ECC decoder. The memory circuit comprises a synchronous static memory. The memory circuit comprises a system for error correction of type Single Error Correction Double Error Detection (SEC-DED) or Double Error Correction, Triple Error Detection (DEC-TED).

公开(公告)号：FR2898223B1

公开(公告)日：2008-07-11

申请号：FR0601832

申请日：2006-03-01

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  JACQUET FRANCOIS ,  DE JONG JEAN JACQUES

IPC: H03K19/003 ,  G06F1/10

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

公开(公告)号：FR2875349B1

公开(公告)日：2007-03-09

申请号：FR0409782

申请日：2004-09-15

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  JACQUET FRANCOIS

IPC: H03K3/356 ,  H01L23/552 ,  H01L23/62 ,  H03K19/007

Abstract: A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.

公开(公告)号：FR2881564A1

公开(公告)日：2006-08-04

申请号：FR0501037

申请日：2005-02-02

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS

IPC: G11C11/419 ,  H01L21/8244

Abstract: Ce circuit intégré de mémoire RAM, en particulier de mémoire SRAM, comprend une matrice de cellules de mémoire disposées entre deux lignes de bits (BL0, BLB0, BL1, BLB1) par l'intermédiaire de deux transistors d'accès (T, T'), les lignes de bits étant destinées l'une à être déchargée et l'autre à être maintenue à un potentiel haut de précharge au cours d'une opération de lecture.La ligne de bits de chaque colonne de la matrice qui est destinée à être maintenue au potentiel haut de précharge est réalisée sous la forme d'au moins deux lignes partielles de bits (BL01, BL02, BLB01, BLB02, BL11, BL12, 13LB11, BLB12), les cellules de mémoire de chaque colonne étant implantées sous la forme de groupes (G1, ..., Gn) de cellules raccordés respectivement aux lignes partielles de bits.

公开(公告)号：FR2875349A1

公开(公告)日：2006-03-17

申请号：FR0409782

申请日：2004-09-15

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  JACQUET FRANCOIS

IPC: H03K3/356 ,  H01L23/552 ,  H01L23/62 ,  H03K19/007

Abstract: Cette bascule protégée contre des pics de courant ou de tension comprend une première porte (P1) de transfert de données recevant, en entrée, des données d'entrée (D, DN) de la bascule, une première cellule de verrouillage maître (C1) raccordée en sortie de la première porte de transfert, une deuxième cellule de verrouillage esclave et une deuxième porte de transfert de données disposée entre les première et deuxième cellules de verrouillage, chaque cellule de verrouillage comprenant un ensemble de noeuds de stockage de données redondants.Les portes de transfert comprennent chacune des moyens (C'1, C'2, C'3, C'4) pour écrire séparément des données dans chaque noeud de stockage.

公开(公告)号：FR2855902A1

公开(公告)日：2004-12-10

申请号：FR0306751

申请日：2003-06-04

Applicant: ST MICROELECTRONICS SA

Inventor： GENEVAUX FRANCK ,  JACQUET FRANCOIS

IPC: G11C7/06 ,  G11C7/12

Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.

公开(公告)号：FR2849260A1

公开(公告)日：2004-06-25

申请号：FR0216558

申请日：2002-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

公开(公告)号：DE69913640D1

公开(公告)日：2004-01-29

申请号：DE69913640

申请日：1999-10-13

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS

IPC: G11C16/04 ,  G11C29/00 ,  G06F11/20