公开(公告)号：DE69932703D1

公开(公告)日：2006-09-21

申请号：DE69932703

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/12

Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

公开(公告)号：DE60119483D1

公开(公告)日：2006-06-14

申请号：DE60119483

申请日：2001-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  GOMIERO ENRICO

IPC: G11C16/08 ,  G11C7/18

公开(公告)号：ITMI20042462A1

公开(公告)日：2005-03-23

申请号：ITMI20042462

申请日：2004-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO

公开(公告)号：DE69528816T2

公开(公告)日：2003-10-23

申请号：DE69528816

申请日：1995-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PARUZZI PAOLA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

公开(公告)号：DE69330401T2

公开(公告)日：2002-06-06

申请号：DE69330401

申请日：1993-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  G11C16/04 ,  H01L29/788

公开(公告)号：DE69330401D1

公开(公告)日：2001-08-09

申请号：DE69330401

申请日：1993-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  G11C16/04 ,  H01L29/788

公开(公告)号：ITTO980516A1

公开(公告)日：1999-12-13

申请号：ITTO980516

申请日：1998-06-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA ,  CREMONESI CARLO ,  CLEMENTI CESARE ,  PIO FEDERICO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

公开(公告)号：ITMI981769D0

公开(公告)日：1998-07-30

申请号：ITMI981769

申请日：1998-07-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.