公开(公告)号：ITTO20000936A1

公开(公告)日：2002-04-08

申请号：ITTO20000936

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  PIERIN ANDREA ,  GREGORI STEFANO ,  KHOURI OSAMA

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/30

公开(公告)号：IT1306964B1

公开(公告)日：2001-10-11

申请号：ITMI990081

申请日：1999-01-19

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  MOTTA ILARIA ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/56 ,  G11C16/26

Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.

公开(公告)号：ITTO20000936D0

公开(公告)日：2000-10-06

申请号：ITTO20000936

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  PIERIN ANDREA ,  GREGORI STEFANO ,  KHOURI OSAMA

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/30

Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

公开(公告)号：ITMI990081A1

公开(公告)日：2000-07-19

申请号：ITMI990081

申请日：1999-01-19

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  MOTTA ILARIA ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/56 ,  G11C16/26

Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.

公开(公告)号：ITMI990080A1

公开(公告)日：2000-07-19

申请号：ITMI990080

申请日：1999-01-19

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  MOTTA ILARIA ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/30

公开(公告)号：ITTO990994D0

公开(公告)日：1999-11-16

申请号：ITTO990994

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.