公开(公告)号：DE69424523T2

公开(公告)日：2001-01-18

申请号：DE69424523

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.

公开(公告)号：DE69424771T2

公开(公告)日：2000-10-26

申请号：DE69424771

申请日：1994-03-22

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

公开(公告)号：DE69424771D1

公开(公告)日：2000-07-06

申请号：DE69424771

申请日：1994-03-22

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

公开(公告)号：DE69328253D1

公开(公告)日：2000-05-04

申请号：DE69328253

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

IPC: G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C16/30

Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage (4) being powered between a first (VPP) and a second (GND) voltage reference and having a first input terminal connected to a resistive divider (2) of the first reference voltage (VPP) and an output terminal fed back to said input through a current mirror (3), and a source-follower transistor (MOUT) controlled by the output and connected to the cells through a programming line (VP). Also provided is a MOS transistor (MG2) which connects to ground the programming line (VP) and a corresponding resistive path (7) connected between the current mirror (3) and the second voltage reference (GND).

公开(公告)号：DE69324258T2

公开(公告)日：1999-09-30

申请号：DE69324258

申请日：1993-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： OLIVO MARCO ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C16/04 ,  H03K21/38 ,  H03K19/21 ,  G11C16/06

Abstract: An end-of-count detecting device (1) for nonvolatile memories, comprising a decoder (2) in the form of a wired OR structure of a number of transistors (3) of the same type, the gate terminals of which are fed with a count signal generated by a counter element (6) and having a predetermined end-of-count value to be detected. A load (7), which may be static, pseudo-dynamic or dynamic, is provided between the common node (4) of the decoder transistors (3) and a reference potential line (VDD); and the decoder output (4) formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.

公开(公告)号：DE69419403D1

公开(公告)日：1999-08-12

申请号：DE69419403

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

Abstract: A load timing circuit (20) including an out-like circuit (21) identical to the output circuits of the memory, so as to present the same propagation time; a simulating signal source (34) for generating a data simulating signal (SP); a synchronizing network (30, 32) for detecting a predetermined switching edge of the data simulating signal (SP) and enabling (35) supply of the signal to the out-like circuit (21) and data supply to the output circuits of the memory; a combinatorial network (29, 30) for detecting propagation of the data simulating signal (SP) to the output of the out-like circuit and disabling the data simulating signal (SP); and a reset element (33) for resetting the timing circuit (20).

公开(公告)号：DE69413793T2

公开(公告)日：1999-04-15

申请号：DE69413793

申请日：1994-01-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G05F3/24 ,  G05F3/26 ,  H03F1/30

Abstract: A current source (20) including a current mirror circuit (1) and an active load circuit (7-9) which form a reference branch, for setting a reference current value (Ir), and a mirroring branch, defining an output current value, connected between supply (30) and ground. A voltage stabilizing transistor (22) is interposed between the current mirror circuit (1) and the load circuit (7-9) in the reference branch only, and is so biased as to maintain its gate terminal (23) at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor (7) is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source (20) may be used to advantage in an oscillator for generating the clock signal of a nonvolatile memory.

公开(公告)号：DE69413793D1

公开(公告)日：1998-11-12

申请号：DE69413793

申请日：1994-01-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G05F3/24 ,  G05F3/26 ,  H03F1/30

Abstract: A current source (20) including a current mirror circuit (1) and an active load circuit (7-9) which form a reference branch, for setting a reference current value (Ir), and a mirroring branch, defining an output current value, connected between supply (30) and ground. A voltage stabilizing transistor (22) is interposed between the current mirror circuit (1) and the load circuit (7-9) in the reference branch only, and is so biased as to maintain its gate terminal (23) at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor (7) is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source (20) may be used to advantage in an oscillator for generating the clock signal of a nonvolatile memory.

公开(公告)号：DE69222249D1

公开(公告)日：1997-10-23

申请号：DE69222249

申请日：1992-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C7/00 ,  G11C5/06

Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

公开(公告)号：IT1253678B

公开(公告)日：1995-08-22

申请号：ITVA910022

申请日：1991-07-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C

Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.