41.
    发明专利
    未知

    公开(公告)号:DE69834499T2

    公开(公告)日:2007-04-19

    申请号:DE69834499

    申请日:1998-12-22

    Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

    42.
    发明专利
    未知

    公开(公告)号:DE69834499D1

    公开(公告)日:2006-06-14

    申请号:DE69834499

    申请日:1998-12-22

    Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

    47.
    发明专利
    未知

    公开(公告)号:IT1236797B

    公开(公告)日:1993-04-02

    申请号:IT2242889

    申请日:1989-11-17

    Abstract: The monolithic vertical-type semiconductor power device comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which there is obtained aP type insulation pocket (3). Such pocket contains N type regions (4, 15) and P type regions (8) which in turn contain N+ type regions (11, 12; 13; 14) and of P type regions (6, 7, 9, 10) which define circuit components (T1, T2, T5) of the device. Insulation pocket (3) is wholly covered by a first metallisation (21, 30) connected to ground. Such metallisation (21, 30) is in turn protected by a layer of insulating material (18) suitable for allowing the crossing of metal tracks (20) or of a second metallisation (31) for the connection of the different components.

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