公开(公告)号：DE60032727D1

公开(公告)日：2007-02-15

申请号：DE60032727

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  ROSSI AUGUSTO ,  BETTI GIORGIO ,  CAZZANIGA MARCO

IPC: G11B5/09 ,  H03H17/02 ,  G11B20/10 ,  H03H17/06

Abstract: The invention relates to a time-continous FIR (Finite Impulse Response) filter whereby a Hilbert transform can be implemented. The filter comprises a cascade of delay cells connected between an input terminal of the filter and an output terminal; constant filter coefficients (cO,...,cn) and a programmable time delay (Td) of the programmable filter cells are provided. The invention also relates to a filtering method effective to enable use of this Hilbert FIR filter structure for processing signals originated by the reading of data from magnetic storage media which employ perpendicular recording.

公开(公告)号：DE60103691D1

公开(公告)日：2004-07-15

申请号：DE60103691

申请日：2001-01-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  CAZZANIGA MARCO ,  CASTELLO RINALDO

IPC: H03F1/42 ,  H03H11/04

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

公开(公告)号：DE69427479D1

公开(公告)日：2001-07-19

申请号：DE69427479

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： BRIANTI FRANCESCO ,  PISATI VALERIO ,  ALINI ROBERTO ,  MOLONEY DAVID

IPC: G05F3/26

公开(公告)号：DE69231151T2

公开(公告)日：2001-02-15

申请号：DE69231151

申请日：1992-08-26

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTELLO RINALDO ,  ALINI ROBERTO ,  REZZI FRANCESCO ,  PISATI VALERIO

IPC: H03F1/32 ,  H03F3/45 ,  H03H11/04

公开(公告)号：ITMI20000391D0

公开(公告)日：2000-02-29

申请号：ITMI20000391

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  VENCA ALESSANDRO ,  CAZZANIGA MARCO

IPC: G06G7/16 ,  G06G7/163 ,  H03D7/14

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.