公开(公告)号：EP1178491A1

公开(公告)日：2002-02-06

申请号：EP00830553.4

申请日：2000-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Gastaldi, Roberto ,  Cappelletti, Paolo ,  Casagrande, Giulio ,  Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory, particularly of the electrically programmable and erasable type such as a flash memory, comprises at least one two-dimensional array (SCT) of memory cells (MC) with a plurality of rows (row0-row511) and a plurality of columns (COL) of memory cells. The columns of the two-dimensional array are grouped in a plurality of packets (CP0-CP1), and the memory cells belonging to the columns of each packet are formed in a respective semiconductor region (4) with a first type of conductivity, this region (4) being distinct from the semiconductor regions (4) with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. It is thus possible to produce memory units of very small dimensions (for example, bytes, words, or long words) which can be erased individually, without excessive overhead in terms of area.

Abstract translation: 半导体存储器，特别是诸如闪存的电可编程和可擦除类型的半导体存储器包括至少一个具有多个行（行0-行511）和多个列的存储器单元（MC）的二维阵列（SCT） （COL）的存储单元。 二维阵列的列被分组为多个分组（CP0-CP1），并且属于每个分组的列的存储器单元以第一类型的导电率形成在相应的半导体区域（4）中，这 区域（4）与半导体区域（4）不同，其中形成属于剩余包的列的存储器单元的第一导电类型。 具有第一导电类型的半导体区域将属于每行的存储器单元组划分为构成可以单独修改的基本存储器单元的多个存储器单元子集。 因此可以产生非常小尺寸的存储单元（例如，字节，单词或长单词），其可以单独擦除，而没有面积方面的过度开销。

公开(公告)号：EP1031991A1

公开(公告)日：2000-08-30

申请号：EP99830108.9

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C11/56

CPC classification number: G11C11/5642

Abstract: The sensing circuits (30, 31, 32) comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit (32) associated with the lowest reference current (I R3 ) amplifies (33b) the cell current more than the other sensing circuits (30, 31) and to the respective reference current (33c). The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current (I R3 ) may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution (I M3 ), retaining the possibility of discriminating between the different logic levels.

Abstract translation: 比较在与参考电流的多个单元中流动的电流的感测电路（30，31，32）不彼此相同，但不同的扩增相比电流。 特别地，感测电路（32）具有最低的参考电流（IR3）放大相关联的（图33B）比其它感测电路的单元电流多（30，31）和所述respectivement参考电流（33C）。 当前动态由此增加，并且能够维持读取电压低，由于最低参考电流（IR3）的固有特性可以是非常靠近或直接叠加在做了立即preceding-存储器单元电流分布的（IM3） ，保持不同的逻辑电平之间进行区分的可能性。

公开(公告)号：EP0961285A1

公开(公告)日：1999-12-01

申请号：EP98830333.5

申请日：1998-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maurelli, Alfonso

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/06 ,  G11C7/062

Abstract: The reading method comprises the steps of: supplying simultaneously two memory cells (F1, F2), both storing a respective unknown charge condition; generating two electrical quantities (Va, Vb), each correlated to a respective charge condition; comparing the two electrical quantities (Va, Vb) with each other; and generating a two-bit signal (01, 02) on the basis of the result of the comparison. The reading circuit comprises a two-input comparator (58) comprising two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter (41). Both the two-input comparator (58) and the current/voltage converter (41) comprise low threshold transistors (49, 50, 65-68).

Abstract translation: 读取方法包括以下步骤：同时提供两个存储相应的未知充电条件的存储单元（F1，F2） 产生两个电量（Va，Vb），每个电量与相应的充电条件相关; 将两个电量（Va，Vb）彼此进行比较; 并根据比较结果生成2比特信号（01,02）。 读取电路包括并联的两个分支的双输入比较器（58），每个分支通过电流/电压转换器（41）连接到相应的存储单元。 双输入比较器（58）和电流/电压转换器（41）都包括低阈值晶体管（49,50,65-68）。

公开(公告)号：EP0928003A2

公开(公告)日：1999-07-07

申请号：EP98114061.9

申请日：1998-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

IPC: G11C8/00 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read.
The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).

Abstract translation: 本发明涉及一种用于电子存储单元装置的行解码电路，特别是在低电源电压应用中，其适用于通过至少一个升压电容器（Cboost）来升压要施加到存储器列的读取电压 包含要读取的存储单元。 电路在第一电源电压基准（Vpcx）和第二接地电位基准（GND）之间供电，并且包括级联连接的逆变器（15,16）的分级结构（13）和逐渐提高读取电压的电路装置 动态级别。 第一装置（Cboost0，D1）被提供用于将读取电压电平升高到等于电源电压（Vpcx）加上阈值电压（Vtp）的值，并且提供第二装置（Cboost1，D2）以提高读取电压电平 达到等于电源电压（Vpcx）加上两倍阈值电压（Vtp）的值。

公开(公告)号：EP0915476A1

公开(公告)日：1999-05-12

申请号：EP97830573.8

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Zammattio, Matteo ,  Ferrario, Donato

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier.
The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract translation: 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便也产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。

公开(公告)号：EP1837993B1

公开(公告)日：2010-01-27

申请号：EP06111477.3

申请日：2006-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: H03K17/10 ,  G11C16/12 ,  H01L27/02

CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

公开(公告)号：EP1837880B1

公开(公告)日：2009-08-26

申请号：EP06113480.5

申请日：2006-05-04

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C8/08 ,  G11C16/12

CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

公开(公告)号：EP1422719B1

公开(公告)日：2009-04-08

申请号：EP03103920.9

申请日：2003-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  MICHELONI, Rino

IPC: G11C11/00

CPC classification number: G11C11/005

公开(公告)号：EP1892600A1

公开(公告)日：2008-02-27

申请号：EP06119456.9

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l.

Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Campardo, Giovanni ,  Micheloni, Rino

IPC: G05F1/56

CPC classification number: G11C5/147 ,  G05F1/565 ,  G11C16/30

Abstract: A voltage regulator (150I) integrated in a chip of semiconductor material is proposed. The regulator has a first input terminal for receiving a first voltage (Vhv) and an output terminal for providing a regulated voltage (Vreg) being obtained from the first voltage, the regulator including: a differential amplifier (205I) for receiving a comparison voltage (Vref) and a feedback signal (Vfb) being a function of the regulated voltage, and for proving a regulation signal (Vr) according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor (MS) having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means (Rpup) between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage (Vdd) being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors (MS1-MS5) being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means (155) for controlling the auxiliary transistors according to the regulated voltage.

Abstract translation: 提出了集成在半导体材料芯片中的电压调节器（150I）。 调节器具有用于接收第一电压（Vhv）的第一输入端子和用于提供从第一电压获得的调节电压（Vreg）的输出端子，所述调节器包括：差分放大器（205I），用于接收比较电压 Vref）和作为调节电压的函数的反馈信号（Vfb），并且根据比较电压和反馈信号之间的比较来证明调节信号（Vr），所述差分放大器具有与 用于接收参考电压的参考端子和第二供电端子，具有用于接收调节信号的控制端子的调节晶体管（MS），以及通过第二端子和第二端子之间的负载装置（Rpup）耦合的导通第一端子和导通第二端子 参考端子和调节器的第一输入端子，调节晶体管的第二端子与输出端子耦合 ，其中所述差分放大器的第二电源端与所述调节器的第二输入端耦合，用于接收低于绝对值中的所述第一电压的第二电压（Vdd），并且其中所述调节器还包括一组 辅助晶体管（MS1-MS5）串联连接在调节晶体管的第二端子和调节器的输出端子之间，以及控制装置（155），用于根据调节电压控制辅助晶体管。

公开(公告)号：EP1845532A1

公开(公告)日：2007-10-17

申请号：EP06112526.6

申请日：2006-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C16/24 ,  G11C7/12 ,  G11C8/10

CPC classification number: G11C8/10 ,  G11C7/12 ,  G11C7/18 ,  G11C16/08 ,  G11C16/24 ,  G11C2207/002

Abstract: A column decoding system (140,150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a biasing voltage to a corresponding bit line, each path including a plurality of series-connected selection transistors (Mi,Mij,Pij) each one having a threshold voltage, and selection means for selecting a path (M1,M11,P11) corresponding to a selected bit line (BL11), the selection means including means for biasing at least one transistor (P12) in each non-selected path (M1,M12,P12) to an open condition to have the corresponding non-selected bit line (BL12) floating; the selection means further includes means for biasing at least one other transistor (M12) in each non-selected path to a drop condition to introduce a voltage drop in the non-selected path higher than the threshold voltage of said one transistor (P12) in absolute value.

Abstract translation: 公开了一种用于选择性地偏置非易失性存储器件（100）的位线（BLij）的列解码系统（140,150）。 位线被逻辑地分组成至少一个分组（PBL）。 对于每个分组，列解码系统包括多个选择路径，每个选择路径每个选择路径用于向对应的位线施加偏置电压，每个路径包括多个串联连接的选择晶体管（Mi，Mij，Pij），每个具有阈值 电压和选择装置，用于选择对应于所选位线（BL11）的路径（M1，M11，P11），所述选择装置包括用于在每个未选择路径（M1，M12）中偏置至少一个晶体管（P12）的装置 ，P12）变为打开状态，使相应的未选位线（BL12）浮置; 所述选择装置还包括用于将每个未选择的路径中的至少一个其他晶体管（M12）偏置到下降条件的装置，以将未选择的路径中的电压降高于所述一个晶体管（P12）的阈值电压 绝对值。