公开(公告)号：JPS62104326A

公开(公告)日：1987-05-14

申请号：JP24520285

申请日：1985-10-31

Applicant: TOSHIBA CORP

Inventor： KISHINO AYANORI ,  NAKAMURA MAKOTO

IPC: H04J3/00 ,  H04B7/15 ,  H04B7/204

Abstract: PURPOSE:To allow a system to recover from abnormality without any deterioration in reliability nor serviceability by transmitting information on the in-use state of a communication circuit from an earth station in a time-division time slot corresponding to a communication circuit that the earth station uses when the system recovers to normal operation after the abnormality occurs. CONSTITUTION:A figure shows that station control processors (SCP) consists of only stations A-D and the state of the transmission of information to an SPC 2 when the station A uses circuits of frequencies f3 and f4, the station C uses circuits of frequencies f1 and fn, and the station D uses a circuit of frequency f4. Thus, one frame of a control circuit is divided into time-division time slots as many as a number (n) of usable circuits and information on the use of the circuits corresponding to the respective time slots is transmitted on a time-division basis to the SCPs which use the circuits. Consequently, even if a specific SCP is congested with in-use circuits, only the time of one-frame transmission is required for a control circuit with an NCP 2, so that the necessary time in normal operation recovery from the abnormality of the system is shortened.

公开(公告)号：JPS6260319A

公开(公告)日：1987-03-17

申请号：JP20000485

申请日：1985-09-10

Applicant: TOSHIBA CORP

Inventor： NAKAMURA MAKOTO ,  SUGIYAMA FUMIO

IPC: H03M13/00

Abstract: PURPOSE:To confirm simply error position of 2-bit or over by comparing a syndrome outputted sequentially from a storage device with a syndrome detected by a syndrome detection means and using an address of the storage device when the both are coincident so as to correct the bit error. CONSTITUTION:The error correction circuit inputs a received data M'(X) to a syndrome detection circuit 11 to obtain a syndrome S(X). On the other hand, a data representing an error position outputted sequentially from a counter 12 is used as an address and a syndrome S'(X) corresponding to the address is generated from a syndrome generation ROM 13. Then the syndromes S'(X) and S(X) are compared by a comparison circuit 14. When the both are coincident, the error bit of the received data M'(X) is inverted by an error bit inverting circuit 15 based on the syndrome generation ROM 13. Thus, the error correction of 2-bit or over is executed without using a complicated algorithm to simplify the circuit constitution.

公开(公告)号：JPS61247984A

公开(公告)日：1986-11-05

申请号：JP8997785

申请日：1985-04-26

Applicant: TOSHIBA CORP

Inventor： TOTOKI TAKASHI ,  NAKAMURA MAKOTO

IPC: H03K3/78 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185

Abstract: PURPOSE:To decrease the number of external terminals necessary for a test and to set an optional test mode freely from outside by inputting specific pattern data to a terminal and generating two kinds of test mode signals, and increasing the number of connections of the shift register in a data shifting circuit. CONSTITUTION:Only one external terminal 16 is provided for a test circuit and the specific pattern data Din is inputted to this terminal 16 to generate two kinds of test mode signals M1 and M2, so the number of external terminals is decreased to one although two terminals are used conventionally. Further, the number of connections of the shift register in the data shifting circuit 15 is increased to increase the number of kinds of test mode signals and an optional test mode is set freely from outside by using only one external terminal.

公开(公告)号：JPS61129913A

公开(公告)日：1986-06-17

申请号：JP25115184

申请日：1984-11-28

Applicant: Nippon Telegr & Teleph Corp ,  Toshiba Corp

Inventor： OTANI KOICHI ,  NAKAMURA MAKOTO

IPC: H04B3/06 ,  H03G3/20

CPC classification number: H03G3/3089

Abstract: PURPOSE:To stabilize the operation of a digital AGC circuit by constituting the input circuit to a variable gain circuit with a square circuit and a digital low pass filter. CONSTITUTION:An output obtained by a level detecting means comprising a square 14 and a digital LPF 15 is fed to a digital subtractor 16, where the said output is subtracted from a reference leve signal ref. Since an output of the LPF 15 is larger (smaller) than the reference level signal ref when the level of a digital signal series outputted to a terminal 13 is larger (smaller) than the reference level, the subtractor 16 outputs a negative (positive) signal. Thus, the gain in a gain memory 18 is decreased (increased) via an adder 17 and the level of the output digital signal series is decreased by multiplying the result with the input digital signal series at the next sampling point of time. Thus, the output is converged into a prescribed level decided by the reference level signal ref. Since the effect of harmonics is not included in the output of the LPF 15, no level fluctuation is caused to the digital signal series outputted to the terminal 13.

Abstract translation: 目的：通过将方波电路和数字低通滤波器构成输入电路到可变增益电路来稳定数字AGC电路的运行。 构成：由包括正方形14和数字LPF 15的电平检测装置获得的输出被馈送到数字减法器16，其中所述输出从参考电平信号ref中减去。 由于当输出到端子13的数字信号串的电平比参考电平大（小））时，LPF15的输出比参考电平信号ref大（小），所以减法器16输出负（正） 信号。 因此，增益存储器18中的增益通过加法器17减小（增加），并且通过将结果与下一个采样时间点的输入数字信号序列相乘来降低输出数字信号序列的电平。 因此，输出被收敛到由参考电平信号ref决定的规定电平。 由于LPF15的输出不包括谐波的影响，所以不会对输出到端子13的数字信号串产生电平变动。

公开(公告)号：JPS58178647A

公开(公告)日：1983-10-19

申请号：JP6052882

申请日：1982-04-12

Applicant: Toshiba Corp

Inventor： TAJIMA MASATO ,  NAKAMURA MAKOTO

IPC: H03M5/04 ,  H03L7/08 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/49

CPC classification number: H04L7/041

Abstract: PURPOSE:To improve the follow-up property of a phase for inputted Manchester modulation data by providing the titled circuit with a control circuit to switch the operation mode of a clock reproducing circuit while considering the state of a reproducing clock in addition to a word synchronizing signal. CONSTITUTION:When Manchester modulation data are inputted from an input terminal 1 to the clock reproducing circuit A, a reproducing clock CKR is generated so as to coincide with the correct phase of the data. A Manchester decoding circuit B decodes an original NRZ data by the reproducing clock CKR and the inputted Manchester modulation data. A word synchronizing circuit C outputs a word synchronizing signal SYNC in accordance with an input data string. The control circuit D outputs a control signal in accordance with the word synchronizing signal SYNC and the reproducing clock CKR to switch the operation mode of the clock reproducing circuit A.

Abstract translation: 目的：通过提供具有控制电路的标题电路来改善输入的曼彻斯特调制数据的相位的跟踪特性，以便在考虑除了字同步之外的再现时钟的状态的同时切换时钟再现电路的操作模式 信号。 构成：当从输入端1向时钟再现电路A输入曼彻斯特调制数据时，产生再现时钟CKR，以便与数据的正确相位一致。 曼彻斯特解码电路B通过再现时钟CKR和输入的曼彻斯特调制数据解码原始NRZ数据。 字同步电路C根据输入数据串输出字同步信号SYNC。 控制电路D根据字同步信号SYNC和再现时钟CKR输出控制信号，以切换时钟再现电路A的工作模式。

公开(公告)号：JPH05235906A

公开(公告)日：1993-09-10

申请号：JP13355492

申请日：1992-05-26

Applicant: TOSHIBA CORP

Inventor： KODAMA TOMOKO ,  NAKAMURA MAKOTO ,  SAITOU TATSUNORI

IPC: H04L1/00 ,  H03M13/15

Abstract: PURPOSE:To eliminate an erroneous symbol with a high probability and to enhance the error correction capability when decoding with elimination and error correction is implemented by selecting a symbol likelihood to be minimum value of m-sets of dot likelihood. CONSTITUTION:The decoder is provided with a bit likelihood calculation means calculating a bit likelihood to each of nXm bits of demodulation signals from a reception signal, a symbol likelihood calculation circuit 25 comparing m-sets of bit likelihoods corresponding to each of n-sets of symbols of a code and outputting a minimum value as the symbol likelihood, and an elimination error correction circuit 27 regarding s-sets (s is a positive integer) in the smaller order of the symbol likelihoods among n-symbols of a demodulation signal as missing symbols and implementing (s-missing and t-error correction) decoding (t is an integer being zero or over). Since the symbol likelihood is set to be minimum value of the m-sets of bit margins, the bit likelihood with least reliability in that of symbols is used for the symbol likelihood as it is, and even when even one bit with lower reliavbility is include, the symbol is used or a missing symbol.

公开(公告)号：JPH04129448A

公开(公告)日：1992-04-30

申请号：JP25154690

申请日：1990-09-20

Applicant: TOSHIBA CORP

Inventor： TANAKA SHUICHI ,  NAKAMURA MAKOTO ,  KODAMA TOMOKO

IPC: H04L27/00 ,  H04L1/00 ,  H04L7/00 ,  H04L27/34

Abstract: PURPOSE:To attain accurate frame synchronization locking at all times by implementing insertion of a frame synchronizing signal and establishment of frame synchronization before differential logic coding and after differential logic decoding respectively. CONSTITUTION:A frame insertion means 1 is arranged before a differential logic coding means 2 in a sender side equipment to insert a frame synchronizing signal to a transmission digital signal before differential logic coding, and a frame synchronization means 10 is arranged after a differential logic decoding means 9 at a receiver side equipment to implement the processing for establishing frame synchronization. Then a signal selection means 8 is provided between an error correction decoding means 6 and the differential logic decoding means 9, and a reception digital signal not implementing error correction decoding is selected when the frame synchronization is not established and the reception digital signal after error correction decoding is selected while the frame synchronization is established to implement the differential logic decoding processing. Thus, frame synchronization is accurately taken.

公开(公告)号：JPH02288752A

公开(公告)日：1990-11-28

申请号：JP11162289

申请日：1989-04-28

Applicant: TOSHIBA CORP

Inventor： KODAMA TOMOKO ,  NAKAMURA MAKOTO

IPC: H04L27/34

Abstract: PURPOSE:To constitute a transparent error correction coding to phase rotation by applying error correction coding independently to sets of each series relating to the decision of a quadrant of a phase plane and other series among m sets of series deciding the arrangement of signal points. CONSTITUTION:Eight sets of digital signal series are inputted from input terminals 1-1-1-8. Two bits inputted from the two input terminals 1-1, 1-2 are fed to a differential logic circuit 2 and the two bits being the result of additive operation are fed to same coders 3, 4 respectively, where they are coded. On the other hand, 8 bits inputted from remaining input terminals 1-3-1-8 are fed to a coder 5, where they are coded, Thus, error correction coding is applied independently to sets of each series relating to the decision of the quadrant of the phase plane and other series to realize the transparent coding to the phase rotation.

公开(公告)号：JPH01276854A

公开(公告)日：1989-11-07

申请号：JP10400188

申请日：1988-04-28

Applicant: TOSHIBA CORP

Inventor： SAKAKIBARA KATSUMI ,  NAKAMURA MAKOTO

IPC: H04L1/16

Abstract: PURPOSE:To recover an error beforehand by encoding both data packet and reproducing packet with a code having an error detecting function and an error correcting function, detecting the error at the time of receiving respective packets and executing the error correcting decoding as a product code after a resending packet is received. CONSTITUTION:A transmitting station 1 provides an encoding means 14 to encode the data of a data packet with an error detecting code and an error correcting code, and a receiving station 2 provides a means to execute the error detection of a receiving signal only concerning the data packet transmitted in a multiple address way and inform a transmitting station whether or not the error is detected and a product code decoding means 28 to execute the error correction as a product code with the resending packet and the already received data packet after a resending packet is received. Thus, as long as the maximum value of the number of errors included in respective receiving data packets is in the range of the error correcting capacity, the error can be recovered without using the resending packet.

公开(公告)号：JPH01168126A

公开(公告)日：1989-07-03

申请号：JP32542687

申请日：1987-12-24

Applicant: TOSHIBA CORP

Inventor： SAKAKIBARA KATSUMI ,  NAKAMURA MAKOTO

IPC: H04J3/00 ,  H04B7/15

Abstract: PURPOSE:To remarkably improve the utilizing efficiency of a satellite line only by storing tentatively an input data into a buffer, and sending only a first data packet only by means of a contention system even to a data series generated intermittently, and transmitting the other data in a reservation system. CONSTITUTION:The data generated in slave stations 13, 14 are stored in a temporary buffer 2, the information representing the number of stores data is added to the head of a packet in compliance with a slot timing from a master station 12 and the number of packet reservations corresponding to the number of stores data is applied. Thus, the efficient transmission is realized independently of the data quantity. Then a QI signal generated by a buffer controller 3 of a slave station is transmitted to a master station in a data packet incorporatedly with an information section signal to eliminate the need for a special slot required to reserve the satellite line. Thus, it is not required to provide the slots for reservation of the number of the earth stations, and the utilizing efficiency of the satellite line is improved flexibly.