公开(公告)号：US10797017B2

公开(公告)日：2020-10-06

申请号：US16283657

申请日：2019-02-22

Applicant: Unimicron Technology Corp.

Inventor： Po-Chen Lin ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Chien-Chou Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/52

Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

公开(公告)号：US20190295984A1

公开(公告)日：2019-09-26

申请号：US16283657

申请日：2019-02-22

Applicant: Unimicron Technology Corp.

Inventor： Po-Chen Lin ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Chien-Chou Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/52

Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

公开(公告)号：US20170025342A1

公开(公告)日：2017-01-26

申请号：US15287729

申请日：2016-10-06

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Yu-Hua Chen ,  Ra-Min Tain

IPC: H01L23/498 ,  H01L23/48 ,  C25D7/12 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49833 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  C25D7/123 ,  H01L21/486 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.

Abstract translation: 提供了包括模制化合物，载体板，芯片，多个导电柱和电路板的芯片封装结构。 载体板包括基板和再分布层。 基板具有第一表面和第二表面。 再分配层设置在第一表面上。 芯片和导电柱设置在再分配层上。 模塑料覆盖芯片，导电柱和再分布层。 电路板与承载板连接，其中电路板设置在模塑料上，使得芯片位于基板和电路板之间，并且芯片和再分布层通过电路板电连接 导电支柱。 由芯片产生的热量通过基板从第一表面传递到第二表面以消散。

公开(公告)号：US09368442B1

公开(公告)日：2016-06-14

申请号：US14583755

申请日：2014-12-28

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Dyi-Chung Hu ,  Yu-Hua Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/3105

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.

Abstract translation: 一种用于制造插入件的方法包括以下步骤。 导电珠填充在基板的盲孔中，并且每个导电珠的焊料层熔化，以在盲孔中形成焊料柱。 每个导电珠的金属球镶嵌在相应的焊料柱中，使得焊接柱和镶嵌在其中的金属球构成导电的通孔。 基板的两个表面被平坦化，使得导电通孔的两个端部分别暴露于基板的两个表面，并分别与基板的两个表面齐平。 在衬底的每个表面处制造再分布层，使得每个导电通孔的两端分别连接重新分布层。 此外，还提供了应用了插入器的插入器和芯片封装结构。

公开(公告)号：US20250096145A1

公开(公告)日：2025-03-20

申请号：US18964695

申请日：2024-12-02

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Chih-Kai Chan ,  Chun-Hsien Chien

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/373 ,  H01L25/03

Abstract: An electronic packaging structure including a first circuit structure and a second circuit structure is provided. An electronic component is disposed between the first circuit structure and the second circuit structure. At least one of the first circuit structure and the second circuit structure (for example, the second circuit structure) has a cavity. The electronic component is embedded in the cavity, and may be encapsulated between the first circuit structure and the second circuit structure.

公开(公告)号：US11808787B2

公开(公告)日：2023-11-07

申请号：US17342550

申请日：2021-06-09

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Kuo Ching Tien ,  Ra-Min Tain

IPC: H05K1/02 ,  H05K1/03 ,  G01R1/06 ,  G01R1/07 ,  G01R1/073 ,  H05K1/11

CPC classification number: G01R1/07342 ,  G01R1/07328 ,  H05K1/112

Abstract: A probe card testing device includes a first sub-circuit board, a second sub-circuit board, a connecting structure layer, a fixing plate, a probe head and a plurality of conductive probes. The first sub-circuit board is electrically connected to the second sub-circuit board by the connecting structure layer. The fixing plate is disposed on the second sub-circuit board and includes an opening and an accommodating groove. The opening penetrates the fixing plate and exposes a plurality of pads on the second sub-circuit board. The accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening. The probe head is disposed in the accommodating groove of the fixing plate. The conductive probes are set on the probe head and in the opening of the fixing plate. One end of the conductive probes is in contact with the corresponding pads, respectively.

公开(公告)号：US20230268257A1

公开(公告)日：2023-08-24

申请号：US17902902

申请日：2022-09-05

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Wen-Yu Lin ,  Tse-Wei Wang ,  Jun-Ho Chen ,  Guang-Hwa Ma

IPC: H01L23/498 ,  H01L23/66 ,  H01Q1/38 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L23/66 ,  H01Q1/38 ,  H01L23/49822 ,  H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/16

Abstract: An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.

公开(公告)号：US20220408554A1

公开(公告)日：2022-12-22

申请号：US17674837

申请日：2022-02-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Chin-Sheng Wang ,  Ra-Min Tain

IPC: H05K1/02 ,  H05K1/18

Abstract: A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.

公开(公告)号：US11410971B2

公开(公告)日：2022-08-09

申请号：US17098436

申请日：2020-11-15

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.

公开(公告)号：US11373927B2

公开(公告)日：2022-06-28

申请号：US16683266

申请日：2019-11-14

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Pei-Chang Huang

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L23/18 ,  H01L23/467 ,  H01L23/14 ,  H01L21/48 ,  H01L23/00

Abstract: A package substrate includes a multilayer circuit structure, a gas-permeable structure, a heat conducting component, a first circuit layer, a second circuit layer and a build-up circuit structure. The gas-permeable structure and the heat conducting component are respectively disposed in a first and a second through holes of the multilayer circuit structure. The first and the second circuit layers are respectively disposed on an upper and a lower surfaces of the multilayer circuit structure and expose a first and a second sides of the gas-permeable structure. The build-up circuit structure is disposed on the first circuit layer and includes at least one patterned photo-imageable dielectric layer and at least one patterned circuit layer alternately stacked. The patterned circuit layer is electrically connected to the first circuit layer by at least one opening. The build-up circuit structure and the first circuit layer exposed by a receiving opening form a recess.