公开(公告)号：JP2011091185A

公开(公告)日：2011-05-06

申请号：JP2009243030

申请日：2009-10-22

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： HORIUCHI MICHIO ,  TOKUTAKE YASUE ,  MATSUDA YUICHI ,  KOBAYASHI TAKESHI ,  DENDA TATSUAKI

IPC: H01L23/32 ,  H01B5/16 ,  H01B13/00 ,  H01R11/01

CPC classification number: H05K3/323 ,  H01L24/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0315 ,  H05K2203/1142 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: PROBLEM TO BE SOLVED: To provide a conducting film used for connection, such that an electronic component including a connection terminal with a narrow pitch is mounted on a wiring board.
SOLUTION: An organic insulating layer 5 is provided with a plurality of linear conductors 3, extending in the thickness direction, and the plurality of linear conductors 3 are exposed from the surface of the organic insulating layer 5 through the organic insulating layer 5. The organic insulating layer 5 is a thermosetting resin layer in an un-cured condition. Here, the diameter of the linear conductor 3 is in the range of 30-1,000 nm, and the pitch of the linear conductor 3 is in the range of 40-1,200 nm.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供用于连接的导电膜，使得在布线板上安装包括具有窄间距的连接端子的电子部件。 解决方案：有机绝缘层5设置有沿厚度方向延伸的多个线性导体3，并且多个线状导体3通过有机绝缘层5从有机绝缘层5的表面露出 有机绝缘层5是未固化状态的热固性树脂层。 这里，直线导体3的直径在30〜1000nm的范围内，线状导体3的间距在40〜1200nm的范围内。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011023626A

公开(公告)日：2011-02-03

申请号：JP2009168596

申请日：2009-07-17

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： HORIUCHI MICHIO ,  TOKUTAKE YASUE ,  MATSUDA YUICHI ,  YAMAZAKI TOMOO ,  SAKAGUCHI YUTA

IPC: H01L23/12 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that has high reliability in connection between semiconductor elements and substrates and is capable of performing high-density packaging, and to provide a method of manufacturing the semiconductor device.
SOLUTION: The semiconductor device includes: the substrate including a plurality of linear conductors passing through from one surface to the other surface; a semiconductor element stuck into a semiconductor element storage hole provided on the substrate; a first insulating layer formed on one surface of the substrate and at the surface side of the semiconductor element; a first wiring layer formed on the first insulating layer and electrically connected to a plurality of linear conductors exposed from one surface of the substrate and within the through-hole and to the semiconductor element via through-holes provided in the first insulating layer; a second insulating layer formed on the other surface of the substrate and at the back side of the semiconductor element; and a second wiring layer formed on the second insulating layer and electrically connected to the plurality of linear conductors exposed from the other surface of the substrate within the through-holes via a through-hole provided in the second insulating layer.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在半导体元件和基板之间的连接具有高可靠性并能够执行高密度封装的半导体器件，并且提供一种半导体器件的制造方法。 解决方案：半导体器件包括：衬底，其包括从一个表面到另一个表面穿过的多个线性导体; 半导体元件粘贴到设置在基板上的半导体元件存储孔中; 形成在所述基板的一个表面上并在所述半导体元件的表面侧的第一绝缘层; 第一布线层，形成在所述第一绝缘层上，并且电连接到从所述基板的一个表面暴露于所述通孔内的多个线状导体，并且经由设置在所述第一绝缘层中的通孔与所述半导体元件连接; 形成在所述基板的另一个表面上和所述半导体元件的背面的第二绝缘层; 以及第二布线层，形成在所述第二绝缘层上，并且经由设置在所述第二绝缘层中的通孔与所述通孔内的所述基板的另一表面露出的多个线状导体电连接。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JPWO2005096442A1

公开(公告)日：2008-02-21

申请号：JP2006511861

申请日：2005-03-29

Applicant: 東海ゴム工業株式会社

Inventor： 久美 別所 ,  久美 別所 ,  佐藤　秀之 ,  秀之 佐藤 ,  明生 佐藤 ,  明生 佐藤 ,  下村　政嗣 ,  政嗣 下村 ,  賢 田中 ,  賢 田中 ,  藪　浩 ,  浩 藪

IPC: H01R11/01 ,  C09J7/02 ,  C09J9/02 ,  C09J11/04 ,  C09J163/00 ,  C09J201/00 ,  H01B5/16 ,  H01B13/00 ,  H01R12/16 ,  H01R13/24 ,  H01R43/00 ,  H05K3/32

CPC classification number: H01R12/7076 ,  C09J7/22 ,  C09J7/26 ,  C09J2201/128 ,  C09J2201/602 ,  H01R13/2414 ,  H05K3/323 ,  H05K2201/0116 ,  H05K2201/09945 ,  H05K2201/10378 ,  Y10T428/24322

Abstract: 接続信頼性を維持しつつ、被接続物のさらなる狭ピッチ化に対応可能であり、また、従来に比較して低コストな異方性導電膜およびその製造方法を提供すること。膜厚方向に貫通した多数の孔部を有し、孔部はハニカム状に配列されるとともに孔部の内壁面は外側方向に湾曲されている、高分子よりなる多孔質膜と、この多孔質膜の孔部内に充填された導電性物質と、多孔質膜の両面に被覆された接着層とを備えた異方性導電膜とする。また、多孔質膜の形成には、水と混ざらず、揮発する有機溶媒中に高分子を溶かし、この高分子溶液をキャストした支持基板を、高湿度条件下に存在させる手法などを用いる。

公开(公告)号：JP2016521464A

公开(公告)日：2016-07-21

申请号：JP2016514062

申请日：2014-05-14

Applicant: エムシー10 インコーポレイテッドMc10,Inc. ,  エムシー10 インコーポレイテッドMc10,Inc.

Inventor： スー、ユン−ユー ,  ワーク、ジョン ,  ジェイ． ダウリング、ケビン ,  ジェイ． ダウリング、ケビン

IPC: H05K1/02 ,  H01L23/12

CPC classification number: H05K1/0283 ,  A61B5/0059 ,  A61B5/6846 ,  A61B2562/164 ,  H01L23/145 ,  H01L23/5386 ,  H01L23/5387 ,  H01L2924/15791 ,  H05K1/189 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/09263 ,  H05K2201/09945

Abstract: 電気接点と電気接点を結合する相互配線とを含む例示的伸縮自在デバイスについて説明する。相互配線は少なくとも1つの入れ子式蛇状特徴を含む蛇行状構成を有する。相互配線は導電性であっても非導電性であってもよい。蛇行状構成は、サーペンタインインサーペンタイン構成を提供する蛇状構造であり得る。

Abstract translation: 例如伸缩装置被描述，其包括互连耦合所述电触点和电触点。 互连具有包括至少一个嵌套的蛇形特征的曲折结构。 甚至互连是导电的也可以是不导电的。 蛇形结构可以是螺旋形结构提供了一个蛇形在蛇形构造。

公开(公告)号：JP5280309B2

公开(公告)日：2013-09-04

申请号：JP2009168596

申请日：2009-07-17

Applicant: 新光電気工業株式会社

Inventor： 道夫 堀内 ,  安衛 徳武 ,  勇一 松田 ,  智生 山崎 ,  勇太 坂口

IPC: H01L23/12

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

公开(公告)号：JP2004282003A

公开(公告)日：2004-10-07

申请号：JP2003315904

申请日：2003-09-08

Applicant: Kinko Denshi Kofun Yugenkoshi ,  欣興電子股▲分▼有限公司

Inventor： SO SHISHO

IPC: H05K1/11 ,  H05K1/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4602 ,  H05K1/0287 ,  H05K1/0298 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/09609 ,  H05K2201/09945

Abstract: PROBLEM TO BE SOLVED: To provide a general purpose core material for a printed circuit board that is suitable for reducing the designing/manufacturing time and the manufacturing cost of the printed circuit board. SOLUTION: The core material is composed of at least one dielectric core layer including first and second surfaces, and a plurality of conducting cylinders connected to the first and second surfaces of the dielectric core layer through the dielectric core layer. The cylinders are arranged either in an array or apart from each other at a constant distance in the dielectric core layer. In addition, each of the first and second surfaces of the dielectric core layer is provided with a conducting layer, respectively, if necessary. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP3547731B2

公开(公告)日：2004-07-28

申请号：JP2002053941

申请日：2002-02-28

Applicant: テッセラ・インコーポレーテッドTessera,Inc.

Inventor： エーレンバーグ、スコット、ジー． ,  カンドロス、イゴール ,  グルーベ、ゲイリー、ダブリュ． ,  ディステファーノ、トーマス、エイチ．

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

公开(公告)号：US08138609B2

公开(公告)日：2012-03-20

申请号：US12832177

申请日：2010-07-08

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract translation: 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US20110095433A1

公开(公告)日：2011-04-28

申请号：US12908943

申请日：2010-10-21

Applicant: Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Tsuyoshi KOBAYASHI ,  Tatsuaki DENDA

Inventor： Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Tsuyoshi KOBAYASHI ,  Tatsuaki DENDA

IPC: H01L23/535 ,  H05K1/02 ,  H01L21/768 ,  B05D5/12

CPC classification number: H05K3/323 ,  H01L24/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0315 ,  H05K2203/1142 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: There is provided a method of manufacturing a conductive film. The method includes: (a) providing an anodized layer having a plurality of through holes extending therethrough in its thickness direction; (b) forming a plurality of linear conductors by filling each of the through holes with a conductive material; (c) forming protection layers on both surfaces of the anodized layer; (d) removing the anodized layer to form a plurality of gaps between the linear conductors; (e) forming an organic insulation layer between the protection layers to fill the gaps with the organic insulation layer; and (f) removing the protection layers.

Abstract translation: 提供了一种制造导电膜的方法。 该方法包括：（a）提供阳极氧化层，其具有在其厚度方向上延伸穿过其中的多个通孔; （b）通过用导电材料填充每个所述通孔来形成多个线性导体; （c）在阳极氧化层的两个表面上形成保护层; （d）去除所述阳极化层以在所述线状导体之间形成多个间隙; （e）在保护层之间形成有机绝缘层，以用有机绝缘层填充间隙; 和（f）去除保护层。

公开(公告)号：US20110013406A1

公开(公告)日：2011-01-20

申请号：US12504627

申请日：2009-07-16

Applicant: Hsiao-Wan KUO

Inventor： Hsiao-Wan KUO

IPC: F21V21/00

CPC classification number: H05K1/142 ,  H05K1/0266 ,  H05K1/0287 ,  H05K3/0052 ,  H05K2201/09936 ,  H05K2201/09945 ,  H05K2201/10106 ,  H05K2201/10287

Abstract: The present invention provides a light emitting diode (LED) circuit board with a multi-directional electrical connection. The board includes a board body with a surface and an assembly plane as well as four sides and corresponding corners, and a plurality of positive and negative electric contacts, separately arranged onto the surface of the board body nearby four sides, and also arranged at intervals. The circuit of the LED circuit board is simplified, helping to facilitate multi-directional electrical connection and expansion, and to improve significantly the paving efficiency of the LED circuit board with better practicability and industrial benefits.

Abstract translation: 本发明提供一种具有多方向电连接的发光二极管（LED）电路板。 板包括具有表面和组装平面以及四个侧面和相应角部的板体，以及分别布置在四个侧面附近的板体表面上的多个正负电触点，并且还间隔地布置 。 LED电路板的电路简化，有助于促进多方向电连接和扩展，并显着提高LED电路板的铺路效率，具有更好的实用性和工业效益。