公开(公告)号：JPS6489349A

公开(公告)日：1989-04-03

申请号：JP14669188

申请日：1988-06-14

Applicant: TANDEM COMPUTERS INC

Inventor： POORU ANDORE HOSU

IPC: H01L23/04 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50

Abstract: PURPOSE: To match two different semiconductor chips by realigning the terminal of a package with the power pad and power plane of the package using vias. CONSTITUTION: A package 10 comprises a package body 12 having a plane provided with pins 16. Pins 16a, 16b project outward from a plane 14 at a position close to a recess 18 where a semiconductor chip is located. A chip 20 is connected through a bonding wire 22 with a pair of power pads 24 for supplying a different voltage to the chip 20. Each pad 24 is connected through an outer via 42 with each pin 16a and each power plane in a group of power planes 34, 36, 38 and 40. Matching is effected by using an inner via in conjunction with a via 42 in the package. One inner via corresponds to one outer via.

公开(公告)号：JPS63274326A

公开(公告)日：1988-11-11

申请号：JP9333088

申请日：1988-04-15

Applicant: TANDEM COMPUTERS INC

Inventor： RARII DEIBUITSUDO RIIBUSU ,  JIEI ARIN ZUWAGAAMAN

IPC: H02H9/02 ,  H02H3/05 ,  H02H3/087

Abstract: A fault tolerant, failsafe power supply system for use in a power supply having an output port coupled to a preselected number of output terminals each providing power at a fixed voltage to an associated load circuit for supplying a fixed voltage to each load circuit. The power supply incudes a ground terminal and a power enable port for receiving an enable signal and turning off the power supply when the enable signal is active. A fault tolerant/failsafe current limit system for preventing an overcurrent condition in a load circuit coupled to a selected output terminal is provided and comprises: a first monitor circuit, external to the power supply and coupling a first output terminal to a first load circuit and supplying current thereto, for generating a first output signal in a first state if an overcurrent condition is detected and in a second state if no overcurrent condition is detected; and a second monitor circuit, external to the power supply and coupling a second output terminal to a second load circuit and supplying current thereto, for generating a first output signal in a first state if an overcurrent condition is detected and in a second state if no overcurrent condition is detected; means, adapted to receive both monitor output signals, for shutting off the power supply to prevent an overcurrent condition unless both monitor circuit output signals are in the second state.

公开(公告)号：JPS60121969A

公开(公告)日：1985-06-29

申请号：JP24038584

申请日：1984-11-14

Applicant: TANDEM COMPUTERS INC

Inventor： KAARU JIEI BEIRII

IPC: H02M1/08 ,  H02M7/5387

公开(公告)号：JPH1125096A

公开(公告)日：1999-01-29

申请号：JP16844596

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： LESLIE HARRY A ,  BIRDSALL DAVID W ,  JAIN ROHIT N ,  YAGHMAI HEDIEH

IPC: G06F12/00 ,  G06F17/30

Abstract: PROBLEM TO BE SOLVED: To efficiently and easily search a data base by designating the range and IN list of many key columns, and constructing each search key by a user. SOLUTION: A computer system 100 is a distributed computer system which is provided with plural computers 102, 104, and 106 mutually connected through a local area network medium and a wide area network medium 108. The value of a predicate designated by a search question is evaluated. The value of the equivalent range is assigned to a key column corresponding to each value of each predicate designated as the value of one range. Also, the value of the equivalent range is assigned to a key column corresponding to each value of each predicate designated as the value of an IN list. Moreover, the value of a certain range is assigned to a key column corresponding to each value of each non-designated predicate. Thus, each search key can be constructed by using those values to be assigned.

公开(公告)号：JPH10320227A

公开(公告)日：1998-12-04

申请号：JP14706698

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To enable efficient processing while relaxing traffic on a processor bus by intelligently limiting the flow of interruption information through the bus between a microprocessor and a processor interface chip(PIC). SOLUTION: On a PIC 16, a write request is inputted to a register PTAIL 204(1) and write data are collected from a Dbus to a write buffer 208. When the buffer 208 is full, a full/empty flag 209 is set to 'full'. When the prescribed amount of data are loaded to the buffer 208, a controller 206 moves the write request from the PTAIL 204(1) to a register PHEAD 204(2). When an Ibus 26 can be used, the write request is moved there and the full/empty flag 209 is set to 'empty'. Therefore, since the write request or the like is asserted on the PIC 16 only at complete time, the Ibus 26 is efficiently used.

公开(公告)号：JPH10320215A

公开(公告)日：1998-12-04

申请号：JP14706798

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F9/46 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To prevent a processor system from being destroyed by the operation of external circuit by intelligently limiting the flow of interruption information between a microprocessor and an interface chip. SOLUTION: Interruptions received through an Ibus 26 are stored in a register 460 based on their interruption numbers. In case of certain interruption, a value passed together with its interruption number is stored together with the setting instruction of interruption in set or reset state and based on a priority mechanism, the priority is determined. An interruption image register 452 maintains the copy of object to exist in an interruption register 450 at a microprocessor 12. The register 452 is updated by the output of master 466 to an internal bus 490, reserve update contents in the register 452 are compared with contents on the internal bus 490 by a comparator 470 and in order to update the register 450, the quantity of traffic on a Pbus 18 is decreased.

公开(公告)号：JPH1011372A

公开(公告)日：1998-01-16

申请号：JP34141296

申请日：1996-12-20

Applicant: TANDEM COMPUTERS INC

Inventor： FISHLER LEONARD R ,  ZARGHAM BAHMAN

IPC: G06F13/00 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To exclude the unrequired copying of data in both of inside a processor and between the processors by steps, etc., for converting a first pointer into plural sub-pointers, dividing a first data stream into plural parts and chaining a protocol header to the respective parts of the first data stream. SOLUTION: The processor 106 includes CPU 110 and a memory 112 and is connected to a disk drive 116 with a disk driver 132 and a disk controller 114. The processor 108 includes CPU 142 and the memory 144 and is connected to LAN 105 with a LAN controller 140. Then, the steps for converting the first pointer into the plural sub-pointers, dividing the first data stream into the plural parts and chaining the protocol header to the respective parts are provided so that the unrequired copying of data is excluded in the processors 106 and 108.

公开(公告)号：JPH09288653A

公开(公告)日：1997-11-04

申请号：JP34141496

申请日：1996-12-20

Applicant: TANDEM COMPUTERS INC

Inventor： RENAADO AARU FUITSUSHIYURAA ,  BAAMAN ZAAGAMU

IPC: G06F11/20 ,  G06F9/54 ,  G06F13/00 ,  H04L29/06 ,  H04L29/12 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To eliminate the unnecessary copying operations of a processor by processing a 1st pointer via a 3rd data source/sink and also chaining the protocol headers at every part of a 1st data stream. SOLUTION: A distributed memory architecture includes plural data sources/ sinks in the forms of CPU 110 and 142 having relative memories which are connected to a network as nodes 102 and also to the data that can be accessed in the network. A descriptor is gotten at a data buffer of the first one of those sources/sinks and then replaced with that of the data buffer of the second source/sink with no transfer of the first buffer. Then the descriptor is replaced with that of the 3rd data source/sink from the second one and, at the same time, the data of the data buffer of the first data source/sink are partly retrieved from the data of the data buffer of the first data source/sink.

公开(公告)号：JPH09244906A

公开(公告)日：1997-09-19

申请号：JP14555296

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： JIEFURII AI ISUWANDEII ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  JIYON DEIIN KOODEINTON ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN EICHI MIRAA ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F11/18 ,  G06F13/24 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To execute the error check of a processor so as not to affect performance at the spot of an interface. SOLUTION: Routers 14A and 14B are connected to sub processor systems 10A and 10B which are one duplex pair of this multiprocessor system and I/O packet interfaces 16A and 16B are connected to the routers. Message packets are copied by the routers and sent by a method for ensuring the synchronization of the both of the pair. Since interruption issued from an I/O element is provided with the information of the cause of the interruption and transmitted by the message packet similarly to other information transfer, protection by the CRC(cyclic redundancy check) of the interruption is performed and the need of deciding the cause from a CPU side is eliminated. The message packet sent through the I/O is provided with the information of an originator and a destination and a reception CPU refers to an external source for permitting access to the memory by an access propriety check and conversion (AVT) chart and checks whether or not the access is allowed.

公开(公告)号：JPH09146870A

公开(公告)日：1997-06-06

申请号：JP16844696

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： MITSUCHIERU RATONAA ,  MAIKERU AARU BUREBINSU ,  DEBITSUDO JIEI SUKOROO ,  RODONII TEI RINPUREHITO

IPC: G06F13/00 ,  H04L29/06

Abstract: PROBLEM TO BE SOLVED: To minimize the cost for maintaining the interaction between a server and a client and system resources to be used. SOLUTION: From a plurality of client nodes 110 and 113 to a specified server node 120, each node delivers the client message having a specified client request. The client messages from a plurality of client nodes 110 and 113 are made to bear data including the both of the data of the specified client request and the data of the relation state of a client and a server. By delivering a plurality of server 190 messages to a plurality of clients 150, the response to the born data is performed. A server message is made to bear data including the data of the specified client request and the data of the relation state of the client and the server. Thus, the piggy backing and the coupling in an execution of the message are used for performing a logical connection between the server and the client.