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公开(公告)号：KR1020030047345A
公开(公告)日：2003-06-18
申请号：KR1020010077814
申请日：2001-12-10
Applicant: 삼성전자주식회사
IPC: H01L21/8242
Abstract: PURPOSE: A method for forming a metal oxide dielectric layer of a semiconductor device is provided to be capable of improving the electric characteristics of the dielectric layer by temporarily stopping the supply of metal source gas. CONSTITUTION: After forming an electrode layer(110) on a substrate(100), a seed layer is formed on the resultant structure by supplying tantalum source gas and oxygen gas in a CVD(Chemical Vapor Deposition) chamber. At this time, the seed layer has a thickness of 5-10 angstrom. Then, the supply of the tantalum source gas is temporarily stopped while keeping on supplying the oxygen gas for improving the characteristics of the seed layer. A tantalum oxide layer(130) having a thickness 150 angstrom is formed on the resultant structure by supplying the tantalum source gas again while supplying the oxygen gas. Then, an upper electrode layer(140) is formed on the tantalum oxide layer(130).
Abstract translation: 目的：提供一种用于形成半导体器件的金属氧化物介电层的方法，其能够通过暂时停止供给金属源气体来改善电介质层的电特性。 构成：在基板（100）上形成电极层（110）之后，通过在CVD（化学气相沉积）室中供应钽源气体和氧气，在所得结构上形成晶种层。 此时，种子层的厚度为5-10埃。 然后，在保持提供氧气以改善种子层的特性的同时暂时停止供给钽源气体。 通过在供给氧气的同时再次供给钽源气体，在所得结构上形成厚度为150埃的氧化钽层（130）。 然后，在氧化钽层（130）上形成上电极层（140）。
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公开(公告)号：KR100365694B1
公开(公告)日：2002-12-26
申请号：KR1020010013751
申请日：2001-03-16
Applicant: 삼성전자주식회사
IPC: H01L21/31
Abstract: 본발명은스텝커버리지와스루풋을향상시킬수 있는, 2단계증착공정에의한금속산화막을형성하는방법및 이를이용한반도체캐패시터의제조방법에관한것이다. 본발명의금속산화막을형성하는방법은하부막상에 1차금속산화막을저온혹은저압공정을수행하여증착하는단계와; 상기 1차금속산화막상에상기 1차탄탈륨산화막의증착조건에비해상대적으로고온혹은고압공정을수행하여 2차탄탈륨산화막을증착하는단계를포함한다. 상기하부막은폴리실리콘막이고상기금속막은탄탈륨산화막인경우, 상기 1차탄탈륨산화막의저온증착공정은 420~460℃에서수행되고저압증착공정은 0.3-3 Torr 의압력에서수행되며, 상기 2차탄탈륨산화막의고온증착공정은 460~500℃에서수행되고고압증착공정은 3-5 Torr 의압력에서수행된다. 상기하부막은금속막이고상기금속산화막은탄탈륨산화막인경우, 상기 1차탄탈륨산화막의저온증착공정은 350~450℃에서수행되고저압증착공정은 0.01-2 Torr 의압력에서수행되며, 상기 2차탄탈륨산화막의고온증착공정은 400~500℃에서수행되고고압증착공정은 0.1-10 Torr 의압력에서수행된다.
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公开(公告)号：KR1020170142698A
公开(公告)日：2017-12-28
申请号：KR1020160076615
申请日：2016-06-20
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L29/66 , H01L21/311 , H01L21/02
CPC classification number: H01L21/823431 , H01L21/31111 , H01L21/31116 , H01L21/823418 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L29/785
Abstract: 집적회로소자는기판의제1 영역에형성되고제1 소스/드레인영역으로채워진제1 리세스가형성된제1 핀형활성영역과, 상기제1 핀형활성영역의하부양 측벽을덮는제1 소자분리막과, 기판의제2 영역에형성되고제2 소스/드레인영역으로채워진제2 리세스가형성된제2 핀형활성영역과, 상기제2 핀형활성영역의하부양 측벽을덮는제2 소자분리막과, 제1 소자분리막위에서제1 핀형활성영역의측벽을덮는핀 절연스페이서를포함한다.
Abstract translation: 该集成电路器件包括：第一元件隔离膜和形成在所述衬底的第一区域上形成须贺第一凹部的第一填充源/漏区的第一销型有源区，覆盖第一支持鳍型有源区和侧壁， 第二隔离膜，第一隔离膜的第二销形的有效区上形成所述衬底的所述第二区域，并且填充有第二源/漏区的形成须贺第二凹部，覆盖所述第一支撑销形的有效区的侧壁 以及覆盖第一针状有源区的侧壁的针状绝缘体隔离物。
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公开(公告)号：KR1020170124748A
公开(公告)日：2017-11-13
申请号：KR1020160054513
申请日：2016-05-03
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L29/66 , H01L29/423
CPC classification number: H01L21/823418 , H01L21/3081 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823821 , H01L21/823828
Abstract: 서로다른거리로이격된게이트전극사이의반도체바디에, 로딩효과(loading effect)가없이에피택셜패턴형성을위한리세스를형성함으로써, 소자성능및 신뢰성을개선할수 있는반도체장치제조방법을제공하는것이다. 상기반도체장치제조방법은제1 영역의기판상에, 제1 거리만큼이격된제1 게이트적층체를형성하고, 제2 영역의상기기판상에, 상기제1 거리보다큰 제2 거리만큼이격된제2 게이트적층체를형성하고, 상기제1 게이트적층체및 상기제1 영역의상기기판을따라제1 블로킹막을형성하고, 상기제1 게이트적층체사이의상기기판상에서상기제1 블로킹막의두께는제1 두께이고, 상기제2 게이트적층체및 상기제2 영역의상기기판을따라제2 블로킹막을형성하고, 상기제2 게이트적층체사이의상기기판상에서상기제2 블로킹막의두께는상기제1 두께와다른제2 두께이고, 상기제1 블로킹막, 제2 블로킹막및 상기기판을제거하여, 상기제1 게이트적층체사이에제1 리세스와, 상기제2 게이트적층체사이에제2 리세스를형성하는것을포함한다.
Abstract translation: 本发明的一个目的是提供一种半导体器件制造方法，该方法能够通过在间隔不同距离的栅电极之间形成用于在半导体本体上形成外延图案的凹部而没有负载效应而提高器件性能和可靠性 。 所述半导体器件制造方法包括：在第一区域的衬底上形成第一栅极堆叠结构第一距离;在第二区域的衬底上形成第一栅极堆叠结构， 以及在第一栅极堆叠体和第一区域的第一区域上形成第一阻挡层，其中第一栅极堆叠层之间的衬底上的第一阻挡层的厚度为 1厚度并沿第二栅极叠层和第二区域的衬底形成第二阻挡膜，并且第二栅极叠层之间的衬底上的第二阻挡膜的厚度大于第一厚度 去除第一阻挡膜，第二阻挡膜和衬底以在第一栅极堆叠体和第二栅极堆叠体之间的第二凹陷之间形成第一凹陷， 它涉及。
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公开(公告)号：KR101739105B1
公开(公告)日：2017-05-23
申请号：KR1020100122918
申请日：2010-12-03
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L21/28123 , H01L29/517 , H01L29/6656
Abstract: 반도체소자의형성방법이제공된다. 반도체소자의형성방법은활성영역을정의하는소자분리막을포함하는기판을준비하고, 활성영역을가로지르는고유전막및 게이트패턴을차례로형성하고, 기판전면에탈산소처리를진행하는것을포함한다.
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Patent Agency Ranking
公开(公告)号：KR1020120106365A
公开(公告)日：2012-09-26
申请号：KR1020110024428
申请日：2011-03-18
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/0922 , H01L21/3003 , H01L21/823807 , H01L21/823828 , H01L29/1054 , H01L29/66651 , H01L29/7843 , H01L21/8238
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce deformities within a PMOS channel by forming a PMOS(P-channel Metal Oxide Semiconductor) channel using silicon-germanium. CONSTITUTION: A substrate including a silicon channel layer and a silicon-germanium channel layer is formed. The silicon channel layer and the silicon-germanium channel layer are formed in order to have a channel direction. Gate structures(GS) are respectively arranged on the silicon channel layer and the silicon-germanium channel layer. A first protective film(160) covering the outcome in which the gate structures are formed is formed. Hydrogen or one among isotopes is inserted in the silicon-germanium channel layer.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过使用硅 - 锗形成PMOS（P沟道金属氧化物半导体）沟道来减少PMOS沟道内的畸变。 构成：形成包括硅沟道层和硅 - 锗沟道层的衬底。 形成硅沟道层和硅 - 锗沟道层以便具有沟道方向。 栅极结构（GS）分别布置在硅沟道层和硅 - 锗沟道层上。 形成覆盖其中形成栅极结构的结果的第一保护膜（160）。 将氢或同位素中的一种插入硅 - 锗通道层中。
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公开(公告)号：KR1020100089023A
公开(公告)日：2010-08-11
申请号：KR1020100007510
申请日：2010-01-27
Applicant: 삼성전자주식회사 , 인터내셔널 비즈니스 머신즈 코오퍼레이션
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/6656 , H01L21/3105 , H01L29/6659 , H01L29/7833 , H01L21/2255
Abstract: PURPOSE: A method for manufacturing a semiconductor device using plasma-dehydrogenation and the semiconductor device are provided to prevent the out-diffusion of dopant included in a substrate by forming dehydrated sidewall-spacers. CONSTITUTION: A semiconductor substrate(100) includes an expanded region(101) and a source/drain region(102). The expanded region and the source/drain region include dopants. The concentration of the dopants in the source/drain is higher than that of the dopants in the expanded region. A gate insulating region(110) and a gate electrode(120) are formed on the semiconductor substrate. A first sidewall spacer(130) and a second sidewall spacer(140) are arranged on both sidewalls of the gate insulating region and the gate electrode.
Abstract translation: 目的：提供一种使用等离子体脱氢和半导体器件制造半导体器件的方法，以通过形成脱水侧壁间隔来防止包含在衬底中的掺杂剂的扩散。 构成：半导体衬底（100）包括扩展区域（101）和源极/漏极区域（102）。 扩展区域和源极/漏极区域包括掺杂剂。 源极/漏极中掺杂剂的浓度高于扩散区域中掺杂剂的浓度。 在半导体衬底上形成栅绝缘区（110）和栅电极（120）。 第一侧壁间隔物（130）和第二侧壁间隔物（140）布置在栅极绝缘区域和栅极电极的两个侧壁上。
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公开(公告)号：KR1020090101831A
公开(公告)日：2009-09-29
申请号：KR1020090022780
申请日：2009-03-17
Applicant: 삼성전자주식회사 , 인피니언 테크놀로지스 아게 , 인터내셔널 비즈니스 머신즈 코오퍼레이션
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7843 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833 , H01L21/32051
Abstract: PURPOSE: A method for forming a field effect transistor with a silicide source/drain contact of a low contact resistor is provided to obtain low susceptibility about the silicide agglomeration. CONSTITUTION: A field effect transistor with a P type source/drain region is formed in a semiconductor substrate(102). A diffusion barrier layer is formed on the source/drain region(104). The silicon nitride is formed on at least part of the diffusion barrier layer extended to the opposite side to the source/drain region(106). The hydrogen is remove from the silicon nitride layer by exposing the silicon nitride layer to the ultraviolet irradiation(108).
Abstract translation: 目的：提供一种用于形成具有低接触电阻器的硅化物源极/漏极接触的场效应晶体管的方法，以获得关于硅化物聚集的低磁化率。 构成：在半导体衬底（102）中形成具有P型源极/漏极区域的场效应晶体管。 在源/漏区（104）上形成扩散阻挡层。 氮化硅形成在扩散阻挡层的至少与源/漏区（106）相反的一侧延伸的部分上。 通过将氮化硅层暴露于紫外线照射（108），从氮化硅层去除氢。
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公开(公告)号：KR1020080096076A
公开(公告)日：2008-10-30
申请号：KR1020070041005
申请日：2007-04-26
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L21/823814 , H01L21/26586
Abstract: A semiconductor device and a method for fabricating the same are provided to improve the carrier mobility of NMOS transistor AND PMOS transistor without adding an additional process for the first and second regions. A method for fabricating a semiconductor device includes the step of providing a semiconductor substrate(100) having a first and second regions; the step of forming a first gate electrode(121a) on the first region, a second gate electrode(122a) on the second region; the step of forming a first source/drain region in the semiconductor substrate by injecting a first conductive foreign materials with a first tilt angle to the first region; the step of forming a second source/drain region in the semiconductor substrate by injecting a second conductive foreign materials with a second tilt angle greater than the first tilt angle to the second region; the step of forming a capping layer on a front side of semiconductor substrate; and the step of annealing the outcome.
Abstract translation: 提供半导体器件及其制造方法以提高NMOS晶体管和PMOS晶体管的载流子迁移率，而不需要为第一和第二区域添加额外的工艺。 一种制造半导体器件的方法包括提供具有第一和第二区域的半导体衬底（100）的步骤; 在第一区域上形成第一栅电极（121a）的步骤，在第二区域上形成第二栅电极（122a） 通过向第一区域注入具有第一倾斜角的第一导电异物，在半导体衬底中形成第一源极/漏极区域的步骤; 通过向第二区域注入具有大于第一倾斜角的第二倾斜角的第二导电异物，在半导体衬底中形成第二源/漏区的步骤; 在半导体衬底的正面上形成覆盖层的步骤; 以及退火结果的步骤。
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公开(公告)号：KR100834737B1
公开(公告)日：2008-06-05
申请号：KR1020060073912
申请日：2006-08-04
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78 , H01L21/8238
Abstract: 반도체 집적 회로 장치의 제조 방법이 제공된다. 반도체 집적 회로 장치의 제조 방법은 반도체 기판 상에 NMOS 트랜지스터를 형성하고, NMOS 트랜지스터 상에 인장 스트레스를 갖는 제1 층간 절연막을 형성하고, 제1 층간 절연막 내에 상기 NMOS 트랜지스터와 연결되는 콘택을 형성하고, 제1 층간 절연막을 탈수소화하여 인장 스트레스를 변화시키는 것을 포함한다.
층간 절연막, 탈수소화, 플라즈마 처리, UV 처리, 열처리
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