公开(公告)号：KR1020130017911A

公开(公告)日：2013-02-20

申请号：KR1020110080646

申请日：2011-08-12

Applicant: 삼성전자주식회사

Inventor： 김지영 ,  진교영 ,  홍형선 ,  황유상 ,  최성관 ,  정현우

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L29/4236 ,  H01L29/42356

Abstract: PURPOSE: A semiconductor device is provided to reduce a leakage current by minimizing a GIDL(Gate Induced Drain Leakage). CONSTITUTION: A semiconductor substrate(100) includes an active region defined by a device isolation layer(110). A first conductive plug(510) is electrically connected to the active region. A second conductive plug(520) electrically connects the active region to a bit line. A buried gate(320) is extended along the trench to fill a part of the trench. The buried gate includes a base part(322a,324a), a first extension part(322b,324b), and a second extension part(322c,324c). The first and the second extension parts are extended along the inner wall of the trench. A capping layer(400) is formed on the buried gate and fills the trench.

Abstract translation: 目的：提供一种半导体器件，通过最小化GIDL（栅极引入漏极泄漏）来减少泄漏电流。 构成：半导体衬底（100）包括由器件隔离层（110）限定的有源区。 第一导电插头（510）电连接到有源区域。 第二导电插头（520）将有源区域电连接到位线。 掩埋栅极（320）沿着沟槽延伸以填充沟槽的一部分。 掩埋栅极包括基部（322a，324a），第一延伸部（322b，324b）和第二延伸部（322c，324c）。 第一和第二延伸部分沿着沟槽的内壁延伸。 在掩埋栅极上形成覆盖层（400）并填充沟槽。

公开(公告)号：KR1020120021398A

公开(公告)日：2012-03-09

申请号：KR1020100073531

申请日：2010-07-29

Applicant: 삼성전자주식회사

Inventor： 정현우 ,  홍형선 ,  오용철 ,  황유상 ,  백철호 ,  김강욱

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827 ,  H01L27/10841

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to secure enough process margins by using a conductive pattern as a buried bit line or a buried word line. CONSTITUTION: An active area is repetitively arranged according to a first direction and a second direction of a substrate(102). A buried word line(WL) is extended according to the first direction while facing each sidewall of the active area of a first group. The active areas of the first group are arranged according to the first direction in a row. A buried bit line(BL) is extended according to the second direction while contacting each sidewall of a second group. The active areas of the second group are arranged according to the second direction in a row.

Abstract translation: 目的：提供半导体器件及其制造方法，以通过使用导电图案作为掩埋位线或掩埋字线来确保足够的工艺余量。 构成：根据衬底（102）的第一方向和第二方向重复地布置有源区域。 掩埋字线（WL）根据第一方向延伸，同时面向第一组的有效区域的每个侧壁。 第一组的有效区域按照第一方向排成一行。 掩埋位线（BL）根据第二方向延伸，同时接触第二组的每个侧壁。 第二组的有效区域按照第二方向排成一列。

公开(公告)号：KR1020110101979A

公开(公告)日：2011-09-16

申请号：KR1020100021383

申请日：2010-03-10

Applicant: 삼성전자주식회사

Inventor： 백철호 ,  홍형선 ,  황유상

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L27/10894 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/4236 ,  H01L27/10885

Abstract: 신뢰성이 향상된 반도체 소자를 개시한다. 상기 반도체 소자는, 기판 상에 소자 분리막에 의하여 상호 분리되며 제 1 방향으로 연장되는 다수의 활성 영역들, 상기 활성 영역의 양측 단부들과 중앙 부위 사이에서 상기 활성 영역 내로 매립되고, 상기 활성 영역과 교차하며, 상기 제 1 방향과 상이한 제 2 방향으로 연장되는 워드 라인들, 상기 활성 영역의 상기 양측 단부들 상에 형성된 제 1 콘택 플러그들, 및 상기 제 1 콘택 플러그들 상에 형성된 제 2 콘택 플러그들을 포함하고, 상기 제 1 콘택 플러그들 각각은, 상기 활성 영역의 양측 단부들과 상기 소자 분리막의 경계와 오버랩 될 수 있다.

公开(公告)号：KR1020110043987A

公开(公告)日：2011-04-28

申请号：KR1020090100765

申请日：2009-10-22

Applicant: 삼성전자주식회사

Inventor： 윤재만 ,  홍형선 ,  전광열 ,  요시다마코토 ,  황덕성 ,  이철

IPC: H01L21/8242 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/10897 ,  H01L27/105 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/66477

Abstract: PURPOSE: A vertical semiconductor device, a memory device, and a manufacturing method thereof are provided to easily implement high integration by including a very small foot print on a substrate. CONSTITUTION: A semiconductor pillar(54) includes an upper impurity region, a lower impurity region, and a vertical channel region. A bit line(56) is arranged on a first sidewall of the lower impurity region. A word line(58) is extended on the second sidewall of the vertical channel region to be vertical to the bit line. The word line is separately arranged on a second mesa. A gate insulation layer is provided between the vertical channel region and the word line. The lower impurity region includes the second mesa on the bit line.

Abstract translation: 目的：提供一种垂直半导体器件，存储器件及其制造方法，以通过在基片上包含非常小的脚印来容易地实现高集成度。 构成：半导体柱（54）包括上杂质区，下杂质区和垂直沟道区。 位线（56）布置在下部杂质区域的第一侧壁上。 字线（58）在垂直沟道区域的第二侧壁上延伸以垂直于位线。 字线分开布置在第二台面上。 在垂直沟道区域和字线之间设置栅极绝缘层。 下部杂质区域包括位线上的第二台面。

公开(公告)号：KR1020100093424A

公开(公告)日：2010-08-25

申请号：KR1020090012599

申请日：2009-02-16

Applicant: 삼성전자주식회사

Inventor： 윤재만 ,  진교영 ,  홍형선 ,  요시다마코토 ,  김봉수

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76834 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L21/76897 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device including a contact plug is provided to easily secure a space for the formation of a contact plug by firstly form contact plugs and form a bit line in a spare space. CONSTITUTION: A semiconductor layer(100) defining a first region and a second region. A first contact plug(120) is electrically connected to the first region. A second contact plug(150) is electrically connected to the second region. A conductive layer(180) is electrically connected to the first contact plug. An insulating layer(160) is located between the conductive layer and the second contact plug.

Abstract translation: 目的：提供一种包括接触插头的半导体器件，通过首先形成接触插头，在备用空间中形成位线，以便容易地确保用于形成接触插塞的空间。 构成：限定第一区域和第二区域的半导体层（100）。 第一接触插塞（120）电连接到第一区域。 第二接触插塞（150）电连接到第二区域。 导电层（180）电连接到第一接触插塞。 绝缘层（160）位于导电层和第二接触插塞之间。

公开(公告)号：KR100825814B1

公开(公告)日：2008-04-28

申请号：KR1020070046193

申请日：2007-05-11

Applicant: 삼성전자주식회사

Inventor： 홍형선 ,  이재구 ,  김동현 ,  권성운 ,  박상준 ,  강남정

IPC: H01L21/28

Abstract: A semiconductor device including a contact barrier is provided to minimize the possibility of generation of a defect in a contact formation process by guaranteeing sufficient insulation margin and a contact area while preventing mutually adjacent conductive line and contact from being short-circuited with each other in forming a contact with a high aspect ratio. A plurality of first conductive lines are extended in a first direction on a semiconductor substrate having a plurality of active regions(110). A plurality of second conductive lines are formed on the first conductive lines, extended in a second direction perpendicular to the first direction. A buried contact(160) is formed on the same level as the second conductive line in a manner that is electrically connected to the active region in the first region confined by two mutually adjacent first conductive lines and two mutually adjacent second conductive lines. A contact barrier(150a) is composed of a plurality of insulation lines extended in at least one of first and second directions over the first conductive line so that the width of the buried contact is confined in at one of the first or second direction. The contact barrier can include a plurality of first insulation lines extended in the first direction so that at least a part of the contact barrier overlaps the first conductive line.

Abstract translation: 提供包括接触屏障的半导体器件，以通过确保足够的绝缘余量和接触面积来最小化产生接触形成过程中的缺陷的可能性，同时防止相互相邻的导电线和接触在形成时相互短路 具有高纵横比的接触。 多个第一导电线在具有多个有源区（110）的半导体衬底上沿第一方向延伸。 多个第二导线形成在第一导线上，在垂直于第一方向的第二方向延伸。 埋入触点（160）以与第二导电线相同的高度形成在与由相互相邻的第一导电线和两个彼此相邻的第二导电线限制的第一区域中的有源区电连接的方式。 接触屏障（150a）由在第一导电线上的第一和第二方向中的至少一个方向延伸的多个绝缘线组成，使得埋入触头的宽度被限制在第一或第二方向中的一个方向。 接触屏障可以包括在第一方向上延伸的多个第一绝缘线，使得接触屏障的至少一部分与第一导电线重叠。