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    Off-line instruction processing system
    52.
    发明专利
    Off-line instruction processing system 未知

    公开(公告)号：DE19848742A1

    公开(公告)日：1999-06-24

    申请号：DE19848742

    申请日：1998-10-22

    Applicant: IBM

    Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

    IPC: G06F9/38 ,  G06F9/28

    Abstract: The system includes an arrangement of physical storage registers which form instances of logical registers. A sequence list associates each logical register with a corresponding physical register, and a connection list associates a physical register which forms an instance of a logical register, to a physical register of an earlier, preceding instance of the same logical register, to form a chain of physical registers according to a sequence of instructions. An Independent claim is provided for a method associating physical registers with logical registers.

    Memory matrix which allows multiple simultaneous writing access with write-through
    53.
    发明专利
    Memory matrix which allows multiple simultaneous writing access with write-through 未知

    公开(公告)号：DE19821581A1

    公开(公告)日：1999-01-07

    申请号：DE19821581

    申请日：1998-05-14

    Applicant: IBM

    Inventor： LOEFFLER PETER ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  TAST HANS-WERNER

    IPC: G11C8/16 ,  G11C7/00 ,  G11C5/02

    Abstract: The matrix uses a quantity of memory cells, along with a process for storing data in one quantity and a process for calling data from another quantity. The quantity of memory allows the functionality of a cell with repeated write connections by means of a quantity of cells with simple write connection and allows multiple simultaneous write accesses. The information, which is contained in the quantity of memory, is presented through all the memories together. It can be retrieved by a read function, which records on a subset of the named quantity. Stored data have three subsets A,B and C, operated on by read and write functions. Writing access is accomplished in three steps. First the contents of all memory, which are not modified, are read. As next values are calculated in a way, which are to be entered in a subset B of the named quantity of memory. The contents and the values of the subset B together represent the desired result. Device for reading contents of subset C of data uses data stored jointly.

    Traducción dinámica de direcciones con calificador con excepción de traducción
    59.
    发明专利
    Traducción dinámica de direcciones con calificador con excepción de traducción 未知

    公开(公告)号：ES2381432T3

    公开(公告)日：2012-05-28

    申请号：ES09714687

    申请日：2009-02-17

    Applicant: IBM

    Inventor： GREINER DAN ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN

    IPC: G06F12/10

    Abstract: Procedimiento para la calificación de una excepción de traducción en una función de traducción dinamica de direcciones, capaz de traducir una dirección virtual a una dirección traducida de un bloque de datos en el almacenamiento (208) principal en un sistema (200) informatico, comprendiendo el procedimiento: obtener una dirección virtual a traducir; traducir dinamicamente la dirección virtual a una dirección real o absoluta de un bloque de datos deseado en el almacenamiento principal; y en respuesta a un evento de interrupción de excepción de traducción que ha ocurrido durante la traducción dinamica de direcciones de la dirección virtual, almacenar en un calificador de excepción de traducción, bits para indicar que dicha excepción de traducción era una de entre una excepción OAT de servidor, que ha ocurrido mientras se ejecutaba un programa de servidor, y una excepción OAT de servidor que ha ocurrido mientras se ejecutaba un programa de cliente; y caracterizado por almacenar en dicho calificador de excepción de traducción bits para indicar cualquiera de entre un tamafo de un marco de cliente al que pertenece dicha excepción OAT de servidor, y un tamafo de un marco de servidor a ser asignado para respaldar dicho marco de cliente

    60.
    发明专利
    未知

    公开(公告)号：AT551652T

    公开(公告)日：2012-04-15

    申请号：AT09714687

    申请日：2009-02-17

    Applicant: IBM

    Inventor： GREINER DAN ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN

    IPC: G06F12/10

    Abstract: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

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