公开(公告)号：DE102004025108A1

公开(公告)日：2005-03-10

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

公开(公告)号：SG70142A1

公开(公告)日：2000-01-25

申请号：SG1998005847

申请日：1998-12-16

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY PETER ,  MANDELMAN JACK ALLAN ,  RADENS CARL J ,  TONTI WILLIAM ROBERT PATRICK

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

公开(公告)号：DE102004025108B4

公开(公告)日：2019-11-28

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Antifuse, die folgendes umfasst:ein Halbleitersubstrat mit einem aktiven Bereich (152; 202; 302), der von einer Grenze (154; 204; 304) einer Flachgrabenisolation umgeben ist;einen über dem Halbleitersubstrat angeordneten und über zumindest einem Teil der Grenze der Flachgrabenisolation liegenden Gateleiter (156; 206; 306);ein zwischen dem Halbleitersubstrat und dem Gateleiter angeordnetes Dielektrikum (157);einen ersten an den Gateleiter gekoppelten Anschluss (158); undeinen zweiten an das Halbleitersubstrat gekoppelten Anschluss (160),wobei der von der Grenze der Flachgrabenisolation umgebene aktive Bereich des Halbleitersubstrates ein längliches Glied (152A; 302A) und mehrere Fingerteile (152B; 302B) enthält, die sich von dem länglichen Glied des aktiven Bereichs erstrecken und quer zu dem länglichen Glied des aktiven Bereichs derart verlaufen, daß der Gateleiter zumindest über einem Teil von zumindest einigen der Fingerteile (152B; 302B) des aktiven Bereichs liegt, undwobei der Gateleiter (156; 206; 306) ein längliches Glied (306A) und mehrere Fingerteile (306B) enthält, die sich von dem länglichen Glied des Gateleiters erstrecken und quer zu dem länglichen Glied des Gateleiters verlaufen.

公开(公告)号：AT407452T

公开(公告)日：2008-09-15

申请号：AT99308160

申请日：1999-10-15

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory cell structure uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor. The buried strap connection between the trench capacitor and the bitline contact (CB) in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar (400) and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off- state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.

公开(公告)号：DE69934357T2

公开(公告)日：2007-09-20

申请号：DE69934357

申请日：1999-06-17

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

公开(公告)号：DE60106256T2

公开(公告)日：2005-10-20

申请号：DE60106256

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  RADENS CARL J

IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/00

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

公开(公告)号：AU2002306174A1

公开(公告)日：2003-12-31

申请号：AU2002306174

申请日：2002-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J ,  WONG ROBERT C

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L23/535 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.