公开(公告)号：JPH1131797A

公开(公告)日：1999-02-02

申请号：JP15505798

申请日：1998-06-03

Applicant: IBM

Inventor： MARK C HEIKY ,  DAVID V HORAK ,  MANDELMAN JACK A ,  WENDEL P NOBLE

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a built-in strap structure which makes a device transfer gate longer in length by the use of a smaller cell region by a method wherein the inside of a storage trench is connected to the rear of an array transfer device, and the strap is arranged in a region which is used only for isolation. SOLUTION: An empty region inside a shallow trench isolation region 82 for a built-in strap which avoids a deep trench collar is used. The layout of a built-in strap indicated by an arrow 80 is carried out in a shallow trench isolation region 82. A space inside a transfer gate 84 between deep trenches 86 is not affected by the built-in strap. By this setup, a built-in strap structure which gives a longer device transfer gate length by the use of a smaller cell region can be obtained.

公开(公告)号：JP2004153250A

公开(公告)日：2004-05-27

申请号：JP2003339550

申请日：2003-09-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SEITZ MIHEL ,  CHUDZIK MICHAEL P ,  MANDELMAN JACK A

IPC: H01L27/108 ,  H01L21/329 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10867 ,  H01L29/66166 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell in which leakage between a buried strap and a buried plate is reduced by decreasing or eliminating parasitic transistors between the buried strap and the buried plate in a trench capacitor storage cell, and to provide a method for forming it.
SOLUTION: A memory cell comprises a trench capacitor containing a trench silicon layer having an upper part and a lower part and the buried plate arranged at the lower part of the trench silicon layer while adjoining it; a FET array comprising a gate part, a drain part, a source part and the buried strap which is combined with one of the source part and the drain part and further combined with the upper part of the trench silicon layer; and a collar, arranged between the buried strap and the buried plate at the periphery of the upper part of the trench silicon layer, which has a reentrant bending part operable so as to decrease an electric field between the buried strap and the buried plate.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004128489A

公开(公告)日：2004-04-22

申请号：JP2003310714

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RADENS CARL J ,  RAMACHANDORA DEIVAKARUNI ,  MANDELMAN JACK A

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To make the interaction between straps smaller than that of the conventional ones. SOLUTION: Each deep trench has its rim in a direction orthogonal to its depth direction. A buried strap 60 extends along the rim. The length of the buried strap 60 is limited to 5-20% of the full length of the rim, and is smaller than one lithography feature size. The buried strap 60, which lies along the rim, is preferably curved and positioned along only one corner of the rim. This structure is useful especially for sub-8F 2 cells. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004064092A

公开(公告)日：2004-02-26

申请号：JP2003280459

申请日：2003-07-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A

IPC: H01L21/8242 ,  H01L21/38 ,  H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10897 ,  H01L27/10864 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator (SOI) method with a pattern for manufacturing a composite integrated circuit having both of a logic circuit part and a buried dynamic random access memory (DRAM) array part.
SOLUTION: The method includes a step to form a buried oxide layer BOX at the logic circuit part 18 of a substrate, which is not masked by a first mask, by injecting oxygen and a step to apply etching to isolation trenches inside the array part 17 and the logic circuit part 18 by a second mask. The first mask can additionally protect the array part 17 when the corners of the device inside the logic circuit part 18 are rounded. The second mask can additionally protect the logic circuit part 18 when the injection inside the array part 17 is executed. A DRAM cell is formed on a bulk part of the substrate in a state of including at least one SOI device having the round corners and at least one DRAM cell having a vertical path gate.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002026146A

公开(公告)日：2002-01-25

申请号：JP2001180648

申请日：2001-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMA ,  JAMMY RAJARAO ,  BYOON WAI KIMU ,  MANDELMAN JACK A ,  SUDO AKIRA ,  TOBBEN DIRK

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for a trench-type capacitor improved in its charge holding capability. SOLUTION: The memory device includes a trench 23 which is formed on a substrate and has an upper part. A collar oxide film 21 is arranged at the upper part of the trench. A collar oxide film includes a pedestal 25. A conductor is charged in the trench. The pedestal reduces a leak of charges in the conductor. The method for forming the memory device, having the collar oxide film having the pedestal collar, is also disclosed.

公开(公告)号：JP2001274262A

公开(公告)日：2001-10-05

申请号：JP2001044604

申请日：2001-02-21

Applicant: IBM

Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A

IPC: H01L21/266 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET array where a high voltage device and a low voltage device are formed on the same substrate. SOLUTION: A method for forming a MOSFET array includes a step for preparing a substrate, a step for forming ac conductor layer on the substrate, a step for injecting dopant species into conductor layer, a step for counter- doping the non-mask part of the doped conductor layer and masking a part of the doped conductor layer and step for forming a depletion conductor region on the substrate. Thus, the substitute of dual gate oxide for MOSFET, in which a high voltage region in the counter-doped part is used for the memory array of DRAM, EDRAM, SRAM and NVRAM and the like, is supplied.

公开(公告)号：JP2000269441A

公开(公告)日：2000-09-29

申请号：JP29109099

申请日：1999-10-13

Applicant: IBM ,  SIEMENS AG

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce a swing below a threshold, a photoelectron degradation, and the sensitivity to a charge existing near the side wall of a device or the like, by forming a second divot shallower than a first divot in a region adjacent to an insulating P well. SOLUTION: This is a buried channel PFET device having a first deep divot 13 on the right side and a second shallow divot 12 on the left side. There is a gate conductor 14 of an N + polysilicon gate conductor and a p-type depletion layer 15 on an N well 11 surrounded by a nitride layer 16. A gate oxide layer 18 separates the gate conductor 14 from the depletion region 15. The nitride layer 16 contacts a shallow trench separation region 10. Contrary to an effect to a surface channel NFET, a parasitic conductance at the edge is produced by the shallow divot 12 in the buried channel PFET. If a gate control is out of control, a gradient below a threshold, an off current, and the reliability of a photoelectron are reduced.

公开(公告)号：JP2000252445A

公开(公告)日：2000-09-14

申请号：JP2000046447

申请日：2000-02-23

Applicant: IBM

Inventor： RAMACHANDRA DIVAKARUUNI ,  EUGENE LEE ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating more stable threshold voltage. SOLUTION: Related to the integrated circuit element and manufacture of it, a gate stack is formed wherein a pattern comprising a storage node diffusion region adjacent to a storage element and a bit line conduct diffusion region 306 facing the storage node diffusion region is formed. An impurity is implanted in the storage node diffusion region and bit line contact diffusion region 306 and an insulator layer is formed on the gate stack with the pattern. A side wall spacer is formed along a part of the gate stack with a pattern adjoining the bit line contact diffusion region 306, and a halo implant 60 is implanted in the bit line contact diffusion region so that no insulator layer blocks the halo implant from the second diffusion region. Further, the integrated circuit element is annealed so that the halo implant 60 is diffused before the impurity is diffused.

公开(公告)号：JPH11274478A

公开(公告)日：1999-10-08

申请号：JP2893699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  WILLIAM H MA ,  MANDELMAN JACK A

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2255 ,  H01L29/66621 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element reducing a short channel effect. SOLUTION: An element has a trench 370 formed in a silicon substrate 305. The channel 380 of the element is formed on the bottom portion of the trench 370. Diffusion layers 310, 320 are formed adjacently to both sides of the trench 370 and are extended along the side walls of the trench 370 and under a part of the trench 370 to form diffusion extension parts 315, 325, whereby each diffusion layer is connected to each edge of the element channel.

Abstract translation: 要解决的问题：提供减少短通道效应的半导体元件。 解决方案：元件具有形成在硅衬底305中的沟槽370.元件的沟道380形成在沟槽370的底部上。扩散层310,320形成在沟槽370的两侧相邻并且延伸 沿着沟槽370的侧壁并在沟槽370的一部分之下形成扩散延伸部分315,325，由此每个扩散层连接到元件沟道的每个边缘。

公开(公告)号：JPH1117001A

公开(公告)日：1999-01-22

申请号：JP16022198

申请日：1998-06-09

Applicant: IBM

Inventor： MARK A JEISO ,  MANDELMAN JACK A ,  TONTI WILLIAM R ,  WORDEMAN MATTHEW R

IPC: H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an SOI(silicon on Insulator)/bulk hybrid semiconductor substrate. SOLUTION: A semiconductor device has SOI regions 120 and bulk regions 122. In single crystal semiconductor regions, conductive spacers 124 are provided to electrically connect the SOI regions to the ground, thereby overcoming the floating body effect. Insulative spacers 126 are formed on the conductive spacers 124 to electrically separate the SOI regions 120 from the bulk regions 122. In manufacturing process of these regions, a sacrificial polishing layer is deposited to the epitaxially grown single crystal bulk regions, and there is no need to selectively grow.