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    A microprocessor having a multiply operation
    51.
    发明专利
    A microprocessor having a multiply operation 未知

    公开(公告)号：HK1057108A1

    公开(公告)日：2004-03-12

    申请号：HK03107535

    申请日：1998-03-16

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F20060101 ,  G06F5/00 ,  G06F9/305 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38

    Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

    A computer system for performing complex digital filters
    52.
    发明专利
    A computer system for performing complex digital filters 未知

    公开(公告)号：AU722030B2

    公开(公告)日：2000-07-20

    申请号：AU1500497

    申请日：1997-02-27

    Applicant: INTEL CORP

    Inventor： FISCHER STEPHEN ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  DULONG CAROLE ,  KOWASHI EIICHI

    IPC: G06F7/48 ,  G06F17/10

    Abstract: A method and apparatus for performing complex digital filters. According to one aspect of the invention, a computer system generally having a transmitting unit, a processor, and a storage device is described. The storage device is coupled to the processor and has stored therein a routine. When executed by the processor, the routine causes the processor to perform a digital filter on unfiltered data items using complex coefficients to generate an output data stream. Execution of the routine causes the processor to perform outer and inner loops. The outer loop steps through corresponding relationships between the complex coefficients and the unfiltered data items. Each of these corresponding relationships is used by the digital filter to generate the output data stream. The inner loop steps the complex coefficients. Within the inner loop, the unfiltered data item corresponding to the current complex coefficient is determined according to the current corresponding relationship. Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number. As a result of the manner in which these eight data elements are stored, the currently calculated complex number represents the product of the current complex coefficient and its corresponding unfiltered data item. The currently calculated complex number is then added to the current output packed data. As a result, the current output packed data stores the sum of the complex numbers generated in the current inner loop.

    MEANS FOR EXECUTING TWO TYPES OF INSTRUCTIONS THAT SPECIFY REGISTERS OF A SHARED LOGICAL REGISTER FILE IN A STACK AND A NON-STACK REFERENCED MANNER
    54.
    发明专利
    MEANS FOR EXECUTING TWO TYPES OF INSTRUCTIONS THAT SPECIFY REGISTERS OF A SHARED LOGICAL REGISTER FILE IN A STACK AND A NON-STACK REFERENCED MANNER 未知

    公开(公告)号：HK1016711A1

    公开(公告)日：1999-11-05

    申请号：HK99101457

    申请日：1999-04-09

    Applicant: INTEL CORP

    Inventor： GLEW ANDREW F ,  VAKKALAGADDA RAMAMOHAN R ,  LIN DERRICK ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F

    Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.

    57.
    发明专利
    未知

    公开(公告)号：DE19681687T1

    公开(公告)日：1998-10-29

    申请号：DE19681687

    申请日：1996-12-10

    Applicant: INTEL CORP

    Inventor： DULONG CAROLE ,  PELEG ALEXANDER D ,  MENNEMEIER LARRY M

    IPC: G06T1/20 ,  G06F15/00

    Abstract: A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine including a transposition routine. The transposition routine manipulates data elements associated with the audio or video signal in transposing an array of n rows of a plurality of data elements. The transposition routine causes the processor to interleave data elements from a first row with data elements from a second row to generate a first result. Data elements from a third row are interleaved with data elements from a fourth row to generate a second result. Then, data elements from the first result are interleaved with data elements from the second result to generate a third result.\!

    59.
    发明专利
    未知

    公开(公告)号：DE19581873T1

    公开(公告)日：1997-12-11

    申请号：DE19581873

    申请日：1995-12-01

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

    Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

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