中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

76 records (took 0.03 seconds)

    POWER ELECTRONIC DEVICE OF MULTI-DRAIN TYPE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND RELATIVE MANUFACTURING PROCESS
    52.
    发明申请
    POWER ELECTRONIC DEVICE OF MULTI-DRAIN TYPE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND RELATIVE MANUFACTURING PROCESS 审中-公开
    集成在半导体基板和相关制造工艺上的多排型电力电子设备

    公开(公告)号：WO2006089725A2

    公开(公告)日：2006-08-31

    申请号：PCT/EP2006001591

    申请日：2006-02-22

    Applicant: ST MICROELECTRONICS SRL ,  SAGGIO MARIO GIUSEPPE ,  FRISINA FERRUCCIO

    Inventor： SAGGIO MARIO GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36

    CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

    Abstract: Power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising: a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlapped on each other, wherein the resistivity of each layer is different from that of the other layers and in that said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24) wherein each doped sub-region (51, 52, 53, 54) is realised.

    Abstract translation: 集成在包括多个元件单元的第一导电类型的半导体衬底（100）上的功率电子器件（30），每个元件单元包括：实现在半导体层上的第二导电类型的体区（40） 20），形成在半导体衬底（100）上的第一类型导电体的第一类型的导电体（50），在所述半导体层（20）内实现的第一类型导电体的列区域（50），其中半导体层（ 20）包括彼此重叠的多个半导体层（21,22,23,24），其中每个层的电阻率不同于其它层的电阻率，并且所述列区域（50）包括多个 掺杂子区域（51,52,53,54），其分别在所述半导体层（21,22,23,24）之一中实现，其中每个掺杂子区域（51,52,53,54） 54）平衡半导体层（21,22,23,24）的电荷量 实现了每个掺杂子区域（51,52,53,54）。

    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES
    53.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES 审中-公开
    用于制造集成在半导体衬底和相应器件中的电子器件的方法

    公开(公告)号：WO2007006504A2

    公开(公告)日：2007-01-18

    申请号：PCT/EP2006006672

    申请日：2006-07-07

    Applicant: ST MICROELECTRONICS SRL ,  FRISINA FERRUCCIO ,  SAGGIO MARIO GIUSEPPE ,  MAGRI ANGELO

    Inventor： FRISINA FERRUCCIO ,  SAGGIO MARIO GIUSEPPE ,  MAGRI ANGELO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

    CPC classification number: H01L29/1095 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7802 ,  H01L29/7835

    Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1, 1a; 10, 11) with wide band gap comprising the steps of: forming a screening structure (3a, 20) on said semiconductor substrate (1, 1a; 10, 11) comprising at least a dielectric layer (2, 20) which leaves a plurality of areas of said semiconductor substrate (1, 1a; 10, 11) exposed, carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a first implanted region (4, 40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a second implanted region (6, 6c; 60, 61) inside said at least a first implanted region (4, 40), carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4, 40; 6, 60).

    Abstract translation: 在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法包括以下步骤：在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20），包括： 至少一个留下所述半导体衬底（1,1a; 10,11）的多个区域的介电层（2,20），所述多个区域暴露在所述半导体衬底（1）中至少进行第一类型的掺杂剂的离子注入 ，1a; 10,11）以形成至少第一注入区域（40,40），在所述半导体衬底（1,1a; 10,11）中至少执行第二类型的掺杂剂的离子注入以形成 在所述至少第一注入区域（4,40）内部的至少一个第二注入区域（6,6c; 60,61）中，执行所述第一类型和第二类型的掺杂剂的激活热过程，其具有适合于完成 所述至少第一和第二植入区域（4,40; 6,60）的形成。

    57.
    发明专利
    未知

    公开(公告)号：DE69833743D1

    公开(公告)日：2006-05-04

    申请号：DE69833743

    申请日：1998-12-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRISINA FERRUCCIO

    IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78

    Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, comprising a first step of forming a first semiconductor layer (41) of a first conductivity type, a second step of forming a first mask (37) over the top surface of the first semiconductor layer (41), a third step of removing portions of the first mask (37) in order to form at least one opening (51) in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer (41) through the at least one opening (51), a fifth step of completely removing the first mask (37) and of forming a second semiconductor layer (42) of the first conductivity type over the first semiconductor layer (41), a sixth step of diffusing the dopant implanted in the first semiconductor layer (41) in order to form a doped region (220) of the second conductivity type in the first and second semiconductor layers (41, 42). The second step up to the sixth step are repeated at least one time in order to form a final edge structure comprising a number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) of the first conductivity type and at least two columns of doped regions (220, 230, 240, 250, 260) of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) and formed by means of superimposition of the doped regions (220, 230, 240, 250, 260) subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther to the high voltage semiconductor device.

    59.
    发明专利
    未知

    公开(公告)号：DE60112726T2

    公开(公告)日：2006-06-14

    申请号：DE60112726

    申请日：2001-05-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COFFA SALVATORE ,  LIBERTINO SEBANIA ,  FRISINA FERRUCCIO

    IPC: H01L31/107 ,  H01L31/0288

    Abstract: The high-gain photodetector (1) is formed in a semiconductor-material body (5) which houses a PN junction (13, 14) and a sensitive region (19) that is doped with rare earths, for example erbium (Er). The PN junction (13, 14) forms an acceleration and gain region (13, 14) separate from the sensitive region (19). The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region (19). Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction (13-14), which is transparent to light, can be captured by an erbium ion in the sensitive region (19), so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.

Patent Agency Ranking