公开(公告)号：JP2005117011A

公开(公告)日：2005-04-28

申请号：JP2004164221

申请日：2004-06-02

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： YU KOKUSHU ,  KAN DAISO ,  CHIN SEIRYU ,  CHANG YI-MING

IPC: H01L23/12 ,  H01L21/76

CPC classification number: H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for a wafer level package. SOLUTION: A plurality of spacer wall structures are formed in a semiconductor wafer or a light transmitting substrate, and the position of a sealant is precisely controlled by the formation of the plurality of spacer wall structures. An element size is determined by positions of a spacer wall and the sealant. Thereby, the distance between the sealant and a photosensitive region is shortened to carry out processes of completing the package of the wafer and scribing. After that, an increase in the number of dies is achieved, and its production capacity is enhanced. In addition to this, the height of the spacer wall is controlled by a semiconductor process, and the uniformity of the gap between the semiconductor wafer and the light transmitting substrate and the stability of the width of the sealant are controlled to enhance its yield. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供晶片级封装的方法和结构。 解决方案：在半导体晶片或透光基板中形成多个间隔壁结构，通过形成多个间隔壁结构来精确地控制密封剂的位置。 元件尺寸由间隔壁和密封剂的位置决定。 由此，缩短了密封剂与感光区域之间的距离，进行了完成晶圆封装和划线的工序。 之后，实现了模具数量的增加，生产能力得到提高。 除此之外，通过半导体工艺控制间隔壁的高度，并且控制半导体晶片和透光基板之间的间隙的均匀性以及密封剂的宽度的稳定性，以提高其产量。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003249555A

公开(公告)日：2003-09-05

申请号：JP2002041178

申请日：2002-02-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SEIYU ,  KA SOGI

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a bar circuit which reduces crosstalks and eddy currents in an integrated circuit. SOLUTION: The bar circuit comprises a first conductivity semiconductor substrate, a second conductivity first elongate well in the semiconductor substrate, and a second conductivity second elongated well in the semiconductor substrate. The second elongated well is under the first elongate well and adjacent to under the first elongated well, thereby connecting it with a barrier to cut off the crosstalks and eddy currents. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002231693A

公开(公告)日：2002-08-16

申请号：JP2001042912

申请日：2001-02-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU CHIA-CHIEH

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a photolithographic and etching method for simplifying process by forming a conductive layer, having a large critical width in situ and forming a shallow trench isolation structure, in which the conductive layer having the larger critical width can be formed on a device having a large step. SOLUTION: In the photolithographic and etching method, a substrate having a conductive layer, a first mask layer and a second mask layer are formed sequentially as the conductive layer, and a patterned photoresist layer is formed on the substrate; with the mask of the photoresist layer, part of the second mask layer is removed to form a second mask layer, having a narrow upper part and a wide bottom part in the side face on the first mask layer; with the mask of the second mask layer, a part of the first mask layer is removed, and the photoresist layer is removed and using the mask of the first mask layer, part of the second mask layer and the conductive layer is removed to form a conductive pattern on the substrate; and finally the first mask layer is removed.

公开(公告)号：JP2002231598A

公开(公告)日：2002-08-16

申请号：JP2001007819

申请日：2001-01-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU CHIA-CHIEH

IPC: G03F7/11 ,  G03F7/42 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide the method of reprocessing photoresist layers for preventing reflection prevention capability from being reduced in an oxysilicon nitride layer. SOLUTION: A silicon chip is provided, where the silicon chip has an insulating layer, bottom-section reflection prevention coating, and the photoresist layer on the coating. The photoresist layer has already been exposed and developed. To remove the greater part of the photoresist layer, wet etching work is carried out. To remove a cured residual photoresist material, low-temperature plasma treatment is executed, where the low-temperature plasma treatment prevents a change in the structure of reflection prevention coating. A new photoresist layer is formed on a bottom-section reflection prevention coating.

公开(公告)号：JP2002111040A

公开(公告)日：2002-04-12

申请号：JP2000286180

申请日：2000-09-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHO SHUNZAI

IPC: H01L27/146 ,  H01L31/10

Abstract: PROBLEM TO BE SOLVED: To provide a photodiode structure for reducing the leakage current of a junction section to approximately 1/10 as compared with a conventional photodiode device, and the manufacturing method of the photodiode structure. SOLUTION: The photodiode structure comprises a second-conductivity-type region 210 that is formed at a specific region from an isolation region 204 adjacent to a substrate 200, and a mask layer for covering at least a peripheral strip near the edge of the isolation region so that the doped second-conductivity- type region is exposed.

公开(公告)号：JP2002041156A

公开(公告)日：2002-02-08

申请号：JP2000212568

申请日：2000-07-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KIM C HARDY

IPC: G05F1/56

Abstract: PROBLEM TO BE SOLVED: To provide a voltage down converter which can be realized by on-chip whose high load performance is improved. SOLUTION: This voltage down converter is provided with a hysteresis generator for combining a hysteresis signal with a reference voltage and an output voltage feedback signal to be applied to a comparator. The hysteresis generator is connected to a control signal for preliminarily announcing when a high current load is activated. The hysteresis signal is switched to a first state before the high current load is activated, and switched over to a second state after the high current load is activated. In the first state, the hysteresis voltage is added to the reference voltage. In the second state, the hysteresis voltage is added to the voltage output feedback signal.

公开(公告)号：JP2001168189A

公开(公告)日：2001-06-22

申请号：JP34550499

申请日：1999-12-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： O SHIMEI

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a dual damascene with a dielectric layer formed on a substrate equipped with a first conductive line and an air gap. SOLUTION: A method for forming a dual damascene structure has a step for forming a dielectric layer on the first conductive line, a step for forming a via-hole opening so as to expose the first conductive line in the dielectric material and the dielectric layer so as to expose the first conductive line, and a step for forming a second conductive line and a via-plug by filling the trench and the via-hole opening with a conductive material.

公开(公告)号：JP2001044385A

公开(公告)日：2001-02-16

申请号：JP21098599

申请日：1999-07-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG

IPC: H01L21/26 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a DRAM capacitor dielectric film having superior dielectric constant. SOLUTION: After a ditantalum pentoxide dielectric film 104 is deposited on a surface of a polysilicon accumulating electrode 102, is the ditantalum pentoxide dielectric film is subjected to two-stage process, and first a remote oxygen plasma process or an UV-ray ozone process is carried out, and next a spike annealing process is carried out. Thus, when the ditantalum pentoxide dielectric film is subjected to two-stage process, the first stage remote oxygen plasma is emitted at relatively lower temperature, and also as the required time of a second stage spike annealing process is extremely short, a thermal history of a manufacture process of a dielectric film can be reduced.

公开(公告)号：JP2000349281A

公开(公告)日：2000-12-15

申请号：JP15531199

申请日：1999-06-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHEN CHIN-RAI ,  RIN TONII ,  CHOU JI-UEN

IPC: H01L29/78 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To lessen a parasitic capacitance between a gate and a drain and another parasitic capacitance between a gate and a source, by a method wherein a MOS transistor with a side slot is provided between a dielectric layer and the left side or right side of a conductive layer located under a metal silicide layer. SOLUTION: A substrate wafer 33, a drain 34, and a source 36 located apart from the drain 34 in a different region on a surface layer are formed on a substrate 31, and an insulating layer 38 is formed on the surface of the substrate 31 between the drain 34 and the source 36. The drain 34, source 36, and metal silicide layer 38 of the gate 40 are covered with a dielectric layer 50, and the dielectric layer 50 is made to function as an insulating layer outside a MOS transistor 29. The MOS transistor 29 is located so as to position two empty side slots 52 on lateral sides of the conductive layer 42 and between the conductive layer 42 and an upper part 44 below the dielectric layer 50 and the metal silicide layer 48.

公开(公告)号：JP2000340762A

公开(公告)日：2000-12-08

申请号：JP13983299

申请日：1999-05-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG ,  RO KATETSU

IPC: H01L27/04 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing the storage node for a capacitor. SOLUTION: After an insulating layer 108 is formed on a substrate 100, and is subjected to an ion-implantation step. Then, the insulating layer is patterned to provide an opening 112 which is exposed as a part of the substrate on the insulating layer 108, and a patterned conductor layer 114 is so formed as to fill the opening on the insulating layer, forming a hemispherical Si particle layer on the conductor layer. The order, in which the ion-implantation step is performed, may be changed as required. In this case, the opening for exposing a part of the substrate is provided at the insulating layer, before being subjected to ion-implantation.