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公开(公告)号：US20230057480A1
公开(公告)日：2023-02-23
申请号：US17810634
申请日：2022-07-04
Inventor： Guangsu SHAO , Deyuan XIAO , Yunsong QIU , Minmin WU
IPC: H01L27/108 , H01L21/311 , H01L21/762
Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.
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公开(公告)号：US20230049171A1
公开(公告)日：2023-02-16
申请号：US17878061
申请日：2022-08-01
Inventor： Guangsu SHAO , Deyuan XIAO , Weiping BAI , Yunsong QIU
IPC: H01L27/108
Abstract: Embodiments provide a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a substrate including a plurality of semiconductor layers arranged at intervals and an isolation layer positioned between adjacent two of the plurality of semiconductor layers, a given one of the plurality of semiconductor layers and the isolation layer being internally provided with trenches, and each of the trenches including a first region, a second region and a third region sequentially distributed; forming a sacrificial layer on an inner wall of the trench in the first region and the second region; forming an insulating layer filling up the trench on a surface of the sacrificial layer; removing the sacrificial layer in the second region, and removing the isolation layer of a first thickness to form voids surrounding the given semiconductor layer.
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公开(公告)号：US20230013070A1
公开(公告)日：2023-01-19
申请号：US17951077
申请日：2022-09-22
Inventor： Guangsu SHAO , Deyuan XIAO , Yunsong QIU , Yuhan ZHU
IPC: H01L27/108
Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes: a semiconductor substrate, where a plurality of columnar active areas are formed on the semiconductor substrate, the plurality of columnar active areas are spaced apart by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; a plurality of third trenches positioned in the semiconductor substrate at bottoms of the second trenches, where the third trenches are recessed to bottoms of the columnar active areas, and a bottom surface of a given one of the third trenches is higher than a bottom surface of the given first trench; and a plurality of metal silicide bit lines extending along the first direction in the semiconductor substrate positioned at the bottoms of the plurality of third trenches and the bottoms of the plurality of columnar active areas.
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64.发明授权公开(公告)号：US12232330B2
公开(公告)日：2025-02-18
申请号：US17805004
申请日：2022-06-01
Inventor： Xiaoguang Wang , Huihui Li , Dinggui Zeng , Jiefang Deng , Kanyu Cao
Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.
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公开(公告)号：US20250031411A1
公开(公告)日：2025-01-23
申请号：US18714965
申请日：2022-12-07
Inventor： Huihui LI , Yunsen ZHANG , Guilei WANG , Chao ZHAO
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H10B12/00 , H10B61/00
Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.
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Patent Agency Ranking
公开(公告)号：US20240412778A1
公开(公告)日：2024-12-12
申请号：US18700634
申请日：2022-12-21
Inventor： Zhengyong Zhu , Bokmoon Kang , Chao Zhao
IPC: G11C11/4096 , G11C11/406 , G11C11/408 , G11C11/4094
Abstract: A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.
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公开(公告)号：US20240381626A1
公开(公告)日：2024-11-14
申请号：US18695254
申请日：2023-08-21
Inventor： Xuezheng AI , Xiangsheng WANG , Guilei WANG , Chao ZHAO , Jin DAI , Wenhua GUI
IPC: H10B12/00
Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.
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68.发明公开公开(公告)号：US20240233810A9
公开(公告)日：2024-07-11
申请号：US18548035
申请日：2021-11-26
Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Inventor： Qi Wang , Huilong Zhu
IPC: G11C11/408 , G11C11/4097
CPC classification number: G11C11/4085 , G11C11/4097
Abstract: A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.
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69.发明公开公开(公告)号：US20240135986A1
公开(公告)日：2024-04-25
申请号：US18548035
申请日：2021-11-26
Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Inventor： Qi Wang , Huilong Zhu
IPC: G11C11/408 , G11C11/4097
CPC classification number: G11C11/4085 , G11C11/4097
Abstract: A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.
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公开(公告)号：US11956943B2
公开(公告)日：2024-04-09
申请号：US18139766
申请日：2023-04-26
Inventor： Zhengyong Zhu , Bokmoon Kang , Guilei Wang , Chao Zhao
IPC: H10B12/00
Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.
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