公开(公告)号：US20140195185A1

公开(公告)日：2014-07-10

申请号：US13735815

申请日：2013-01-07

Applicant: KIONIX, INC.

Inventor： Erik ANDERSON

IPC: G01P3/44 ,  G06F17/00 ,  G01P21/02 ,  G01P15/18

CPC classification number: G01P3/44 ,  G06F17/00

Abstract: A system and method for estimating angular velocity are provided. The system and method use an accelerometer and magnetometer to estimate an angular velocity in place of a gyroscope in 9-axis sensor fusion to estimate angular orientation. The final angular velocity estimate is constructed from two partially independent angular velocity estimates, one using only magnetometer measurements and the other using only accelerometer measurements. The unobservable portion of each partial angular velocity estimate is provided by a projection from a third complete estimate that uses both accelerometer and magnetometer data.

Abstract translation: 提供了一种用于估计角速度的系统和方法。 该系统和方法使用加速度计和磁力计估计9轴传感器融合中的陀螺仪的角速度来估计角度定向。 最终角速度估计由两个部分独立的角速度估计构成，一个仅使用磁强计测量，另一个仅使用加速度计测量。 每个部分角速度估计的不可观察部分由来自使用加速度计和磁力计数据的第三完整估计的投影提供。

公开(公告)号：US20030178075A1

公开(公告)日：2003-09-25

申请号：US10366087

申请日：2003-02-12

Applicant: KIONIX, INC.

Inventor： James E. Moon ,  Lincoln C. Young

IPC: F15C001/06

CPC classification number: B81C1/00071 ,  B01F5/061 ,  B01F5/0644 ,  B01F13/0059 ,  B01F2005/0621 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00828 ,  B01J2219/00831 ,  B01J2219/00864 ,  B01J2219/00934 ,  B01L3/5027 ,  B81B2201/058 ,  B81B2203/0338 ,  B81B2203/0376 ,  G01N30/6078 ,  G01N30/6095 ,  Y10T137/0402 ,  Y10T137/2224

Abstract: A method for etching an ultra-shallow channel includes using an etch process that is selective for one material to etch a different material in order to achieve a very precise channel depth in the different material. Channels as shallow as 10 nm can be fabricated in silicon with precision of 5 nm or better using the method. Stepped channels can be fabricated where each segment is a different depth, with the segments being between 10 nm and 1000 nm in depth. The method is applied to create a fluidic channel which includes a channel substrate to which is bonded a lid substrate to confine fluids to the fluidic channels so fabricated.

Abstract translation: 蚀刻超浅沟道的方法包括使用对一种材料选择性蚀刻不同材料的蚀刻工艺，以便在不同材料中实现非常精确的沟道深度。 使用该方法可以在5nm或更好的精度的硅中制造浅10nm的通道。 可以制造阶梯通道，其中每个段是不同的深度，其中该段的深度在10nm和1000nm之间。 该方法被应用于产生流体通道，该流体通道包括通道基底，将通道基底与盖基底结合，将流体限制在如此制造的流体通道上。

公开(公告)号：US20020092822A1

公开(公告)日：2002-07-18

申请号：US10003851

申请日：2001-11-02

Applicant: Kionix, Inc.

Inventor： James E. Moon ,  Timothy J. Davis ,  Gregory J. Galvin ,  Kevin A. Shaw ,  Paul C. Waldrop ,  Sharlene A. Wilson

IPC: C23F001/00

CPC classification number: B05B5/00 ,  H01J49/0018 ,  H01J49/167 ,  Y10S438/942

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as nulllatent maskingnull, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as nullsimultaneous multi-level etching (SMILE)null, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as nulldelayed LOCOSnull, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes. The fourth aspect provides a process sequence that incorporates all three fundamental aspects to fabricate an integrated liquid chromatography (LC)/electrospray ionization (ESI) device. The fifth aspect provides a process sequence that incorporates two of the fundamental aspects to fabricate an ESI device. The sixth aspect provides a process sequence that incorporates two of the fundamental aspects to fabricate an LC device. The process improvements described provide increased manufacturing yield and design latitude in comparison to previously disclosed methods of fabrication.

Abstract translation: 公开了本发明的三个基本和三个派生方面。 三个基本方面各自公开了可以整合到完整过程中的过程序列。 第一方面，被指定为“潜屏蔽”，定义了在固定材料（例如氧化硅）中的掩模，该掩模在定义之后被保持为静止，而执行中间处理操作。 然后将潜在氧化物图案用于掩模蚀刻。 指定为“同时多级蚀刻（SMILE）”的第二方面提供了一种处理顺序，其中在蚀刻到下面的材料中第一图案可相对于第二图案被赋予高级开始，使得第一图案可以是 蚀刻成更深，更浅或与第二图案相同的深度。 指定为“延迟LOCOS”的第三方面提供了在过程的一个阶段定义接触孔图案的方法，然后在稍后阶段使用限定的图案来打开接触孔。 第四方面提供了一个整合三个基本方面来制造液相色谱（LC）/电喷雾离子化（ESI）装置的方法。 第五方面提供了一种结合两个基本方面来制造ESI装置的过程序列。 第六方面提供了一种结合两个基本方面来制造LC器件的过程序列。 与先前公开的制造方法相比，所描述的工艺改进提供了增加的制造产量和设计自由度。

公开(公告)号：US11313877B2

公开(公告)日：2022-04-26

申请号：US16446433

申请日：2019-06-19

Applicant: Kionix, Inc.

Inventor： Andrew Hocking

IPC: G01P15/13 ,  B81B7/02

Abstract: A MEMS includes, in part, a parallel plate capacitor, a proofmass adapted to be displaced by a first distance from a rest state in response to a first voltage applied to the capacitor, and a piezoelectric material adapted to generate a second voltage in response to an external force applied to the MEMS. The second voltage causes the MEMS to transition from a standby mode to an active mode of operation. The proofmass is displaced by a second distance in response to the external force thereby causing the piezoelectric material to generate the second voltage. A spring couples the proofmass to the piezoelectric material, and a transistor turns on in response to the second voltage thereby causing the MEMS to transition to the active mode of operation. The proofmass returns to the rest state when the MEMS is in the active mode of operation.

公开(公告)号：US10829366B2

公开(公告)日：2020-11-10

申请号：US15941465

申请日：2018-03-30

Applicant: Kionix, Inc.

Inventor： Scott G. Adams ,  Charles W. Blackmer

IPC: H01L29/40 ,  B81B7/00 ,  B81C1/00 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

Abstract: Disclosed is a method of forming an interconnect in a substrate having a first surface and a second surface. The method includes forming an insulating structure abutting the first surface and defining a closed loop around a via in the substrate and forming an insulating region abutting the second surface such that the insulating region contacts the insulating structure and separates the via from a bulk region of the substrate. Forming the insulating structure includes etching the substrate beginning from the first surface to form a trench, filling the trench to form a seam portion, and converting a first portion of the substrate to a first solid portion to form the closed loop.

公开(公告)号：US20190263656A1

公开(公告)日：2019-08-29

申请号：US16407045

申请日：2019-05-08

Applicant: Kionix, Inc.

Inventor： Martin Heller ,  Toma Fujita

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/02 ,  B32B15/20 ,  B32B15/04

Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.

公开(公告)号：US10315915B2

公开(公告)日：2019-06-11

申请号：US14790378

申请日：2015-07-02

Applicant: Kionix, Inc.

Inventor： Scott G. Adams ,  Charles W. Blackmer

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

Abstract: Disclosed are systems, methods, and computer program products for electronic systems with through-substrate interconnects and mems device. An interconnect formed in a substrate having a first surface and a second surface, the interconnect includes: a bulk region; a via extending from the first surface to the second surface; an insulating structure extending through the first surface into the substrate and defining a closed loop around the via, wherein the insulating structure comprises a seam portion separated by at least one solid portion; and an insulating region extending from the insulating structure toward the second surface, the insulating region separating the via from the bulk region, wherein the insulating structure and insulating region collectively provide electrical isolation between the via and the bulk region.

公开(公告)号：US20180282154A1

公开(公告)日：2018-10-04

申请号：US15685957

申请日：2017-08-24

Applicant: Kionix, Inc.

Inventor： Martin Heller ,  Jonah deWall ,  Andrew Hocking ,  Kristin Lynch ,  Sangtae Park

IPC: B81C1/00

CPC classification number: B81C1/00269 ,  B81C2201/013 ,  B81C2201/0171 ,  B81C2201/0197 ,  B81C2201/05 ,  B81C2203/0118

Abstract: A method of fabricating a semiconductor device, includes, in part, growing a first layer of oxide on a surface of a first semiconductor substrate, forming a layer of insulating material on the oxide layer, patterning and etching the insulating material and the first oxide layer to form a multitude of oxide-insulator structures and further to expose the surface of the semiconductor substrate, growing a second layer of oxide in the exposed surface of the semiconductor substrate, and removing the second layer of oxide thereby to form a cavity in which a MEMS device is formed. The process of growing oxide in the exposed surface of the cavity and removing this oxide may be repeated until the cavity depth reaches a predefined value. Optionally, a multitude of bump stops is formed in the cavity.

公开(公告)号：US10053360B1

公开(公告)日：2018-08-21

申请号：US15685879

申请日：2017-08-24

Applicant: Kionix, Inc.

Inventor： Martin Heller

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00047 ,  B81C1/00095 ,  B81C2201/0109 ,  B81C2201/0115 ,  B81C2201/0132 ,  B81C2201/0171 ,  B81C2201/0178

Abstract: A method of processing a semiconductor substrate having a first conductivity type includes, in part, forming a first implant region of a second conductivity type in the semiconductor substrate where the first implant region is characterized by a first depth, forming a second implant region of the first conductivity type in the semiconductor substrate where the second implant region is characterized by a second depth smaller than the first depth, forming a porous layer within the semiconductor substrate where the porous layer is adjacent the first implant region, and growing an epitaxial layer on the semiconductor substrate thereby causing the porous layer to collapse and form a cavity.

公开(公告)号：US20170001858A1

公开(公告)日：2017-01-05

申请号：US14790378

申请日：2015-07-02

Applicant: Kionix, Inc.

Inventor： Scott G. ADAMS ,  Charles W. BLACKMER

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: B81B7/007 ,  B81B2207/096 ,  B81C1/00301 ,  B81C2201/013 ,  H01L21/30604 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329

Abstract: Disclosed are systems, methods, and computer program products for electronic systems with through-substrate interconnects and mems device. An interconnect formed in a substrate having a first surface and a second surface, the interconnect includes: a bulk region; a via extending from the first surface to the second surface; an insulating structure extending through the first surface into the substrate and defining a closed loop around the via, wherein the insulating structure comprises a seam portion separated by at least one solid portion; and an insulating region extending from the insulating structure toward the second surface, the insulating region separating the via from the bulk region, wherein the insulating structure and insulating region collectively provide electrical isolation between the via and the bulk region.

Abstract translation: 公开了用于具有贯穿衬底互连和mems器件的电子系统的系统，方法和计算机程序产品。 形成在具有第一表面和第二表面的基底中的互连，所述互连包括：体区域; 从第一表面延伸到第二表面的通孔; 绝缘结构，其延伸穿过所述第一表面进入所述基底并围绕所述通孔限定闭合环，其中所述绝缘结构包括由至少一个实心部分分开的接缝部分; 以及从所述绝缘结构朝向所述第二表面延伸的绝缘区域，所述绝缘区域将所述通孔与所述主体区域分离，其中所述绝缘结构和绝缘区域共同地提供所述通孔和所述主体区域之间的电隔离。