公开(公告)号：EP0786778A1

公开(公告)日：1997-07-30

申请号：EP96830024.4

申请日：1996-01-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Villa, Corrado ,  Bez, Roberto ,  Cantarelli, Daniele ,  Dallabora, Marco

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode, provides for coupling the control electrode to a first voltage supply, coupling the first electrode to a second voltage supply, the first voltage supply and the second voltage supply being suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.

Abstract translation: 一种用于在电可编程和可擦除的具有控制电极，在电绝缘的电极和第一电极的非易失性存储器单元擦除方法，提供用于控制电极耦合到第一电压源，所述第一电极耦合到第二电压供应 时，第一电源电压和第二电压供应适于引起的电绝缘电极和第一电极之间的电荷隧穿。 该方法提供了恒定的电流到所述第二电源电压和所述存储单元的第一电极之间，用于的存储单元的擦除时间的至少一部分流动，恒定电流具有一个预定值。

公开(公告)号：EP0785570A1

公开(公告)日：1997-07-23

申请号：EP96830021.0

申请日：1996-01-22

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Rolandi, Paolo

IPC: H01L21/00 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11543

Abstract: In a fabrication process of a nonvolatile memory device natural or low threshold transistors usable in the peripheral circuitry are economically fabricated by exploiting the MATRIX mask that is commonly used for patterning the interpoly dielectric layer for defining the channel length of the natural transistors by patterning said interpoly dielectric layer also over the channel area of the natural transistor, outside the matrix area. The so predefined interpoly dielectric is thereafter exploited as a mask of the polysilicon of first level during the patterning step of the polysilicon of second level. Electrical continuity between the polysilicon of second level and the so patterned gate of polysilicon of first level being established over the field oxide adjacent to the active area of the natural transistor.

Abstract translation: 在外围电路一起使用的非易失性存储器件的天然或低阈值晶体管的制造工艺在经济上是通过利用MATRIX掩模制造并通常用于为限定通过图案间（interpoly）所述的天然晶体管的沟道长度图案化间介电层 电介质层，从而在自然晶体管的沟道区域中，矩阵区域之外。 此后将这样的预定义间电介质被利用作为第一级的多晶硅的过程中的第二级多晶硅的图案化步骤的掩模。 正在建立过的第二级的多晶硅和第一级的多晶硅，从而图案化的栅极之间的电连续性的场氧化物毗邻天然晶体管的有源区。

公开(公告)号：EP0782235A1

公开(公告)日：1997-07-02

申请号：EP95830550.0

申请日：1995-12-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Pulvirenti, Francesco ,  Bontempo, Gregorio ,  Gariboldi, Roberto

IPC: H02H1/00 ,  H03K17/082

CPC classification number: H03K17/0822 ,  H03K2017/0806 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.
The method of this invention provides for:

the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; and
the utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

The power transistor (PW) is turned on again, and the current limiting circuit (4) inhibited, by the following steps:

a) generating an electric signal which is substantially proportional to the voltage appearing at the output terminal (OUT) of the actuator;
b) driving the control terminal (G) of the power transistor (PW) by means of said electric signal, and causing said transistor to conduct, while simultaneously disabling the current limiting circuit (4) when the output voltage exceeds a predetermined threshold; and
c) allowing the transient energy to be dissipated to the power transistor (PW).

Abstract translation: 本发明的目的在于提供一种用于保护功率执行器的输出级以防止浪涌型电压瞬变的方法和电路。 特别地，它提供了针对包含在执行器的输出级中的功率晶体管的国际标准IEC 801-5所述类型的电压浪涌瞬变的保护。 本发明的方法提供：功率晶体管（PW）本征二极管（DP）用于在正瞬变期间将瞬态能量倾倒到一个供电发生器端子; 以及在负瞬态期间将功率晶体管（PW）恢复特性应用于导通状态以将能量倾倒在其中，同时抑制电流限制功能。 功率晶体管（PW）再次导通，并且限流电路（4）通过以下步骤来禁止：a）产生基本上与致动器的输出端（OUT）处出现的电压成比例的电信号 ; b）通过所述电信号驱动功率晶体管（PW）的控制端（G），并使所述晶体管导通，同时当所述输出电压超过预定阈值时禁止所述限流电路（4）; 以及c）允许瞬态能量被耗散到功率晶体管（PW）。

公开(公告)号：EP0782184A1

公开(公告)日：1997-07-02

申请号：EP95830551.8

申请日：1995-12-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pionelli, Renato ,  Corno, Marziano

IPC: H01L21/56 ,  H01L23/433 ,  H01L23/495

CPC classification number: H01L23/49541 ,  H01L21/565 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a heat-dissipating and supporting structure (16) for a semiconductor electronic device to be encapsulated within a molded plastic package, of the type having an insulated inner heat sink. In particular, it comprises a heat-sink element (18) which has a first largest surface to be insulated by means of a plastic material layer with a first thickness, and a second largest surface, opposite from the first, to be insulated by means of a layer of plastic material with a second thickness which is thin compared to the first thickness; and a leadframe (17) consisting of a metal strip attached to the heat-sink element (18) on the same side as the first largest surface and comprising an peripheral holder structure (7) located outboard of the heat-sink element (18).
Formed in a portion of a side surface (19) of the heat-sink element (18), is a relief (20) which has mouths located on the first and second largest surfaces of the heat-sink element (18), the mouth formed on the first largest surface being closed by an obstructing means (21) which extends to the heat-sink element (18) outside, toward the peripheral structure (7), such as to only leave a slit (A2) open between the obstructing means (21) and said peripheral structure (7) of the leadframe (17) next to the first largest surface of the heat-sink element and leave the mouth toward the second largest surface open wide.
For the purpose of this invention, the spoiler and relief are provided at a mold gate for introducing the molten plastic material during the molding process. Thus, the relief is formed in the proximity of a side corner edge of the heat sink.

Abstract translation: 本发明涉及一种用于半导体电子器件的散热和支撑结构（16），其被封装在模制塑料封装内，该类型具有绝热的内部散热器。 特别地，它包括散热元件（18），该散热元件（18）具有通过具有第一厚度的塑料材料层被绝缘的第一最大表面和与第一厚度相反的第二最大表面， 具有与第一厚度相比薄的第二厚度的塑料材料层; 以及引线框架（17），其由与所述散热元件（18）在与所述第一最大表面相同的一侧上附接的金属条构成，并且包括位于所述散热元件（18）外侧的外围保持器结构（7） 。 形成在散热元件（18）的侧表面（19）的一部分中的是具有位于散热元件（18）的第一和第二最大表面上的口的浮雕（20），嘴 形成在第一最大表面上，被阻挡装置（21）封闭，所述阻塞装置（21）向外部结构（7）向外延伸到散热元件（18），从而仅在狭缝（A2）之间留下狭缝（A2） 所述引线框架（17）的所述周边结构（7）与所述散热元件的所述第一最大表面相邻的装置（21）和所述外围结构（7），并且朝向所述第二最大表面敞开宽度。 为了本发明的目的，扰流器和浮雕设置在模具浇口处，以在模制过程中引入熔融塑料材料。 因此，浮雕形成在散热器的侧角边缘附近。

公开(公告)号：EP0782148A2

公开(公告)日：1997-07-02

申请号：EP96830245.5

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Dallabora, Marco ,  Villa, Corrado ,  Bartoli, Simone ,  Defendi, Marco

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459

Abstract: The invention concerns a method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which comprises a matrix of memory cells divided into sectors and programmable in a byte mode. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied.
The invention further provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.

Abstract translation: 本发明涉及在编程和电可编程的擦除的步骤避免干扰的方法，半导体集成电路的非易失性存储器装置，其包括存储器单元分成扇区和可编程以字节模式的矩阵。 的字节的内容的操作验证要被编程，对于每个单独的位被执行时，第一编程脉冲施加之前就被设置。 本发明还提供了几个扇区的期间擦除步骤的擦除并行，并为矩阵中的每个扇区的擦除步骤的验证。 如果验证表明做了一个部门被擦除，该行业是应用没有进一步的擦除脉冲。

公开(公告)号：EP0782144A1

公开(公告)日：1997-07-02

申请号：EP95830552.6

申请日：1995-12-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Daniele, Vincenzo

IPC: G11C11/00 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17708 ,  H03K19/1736

Abstract: A monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type. which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed.
Preferably, the flash memory cells are Fowler-Nordheim Effect cells.

Abstract translation: 具有基本模块单片集成的可编程器件电连接由闪存类型的存储器单元的手段。 哪些小区允许的基本模块的信号线之间的信号路径进行编程和重新编程。 优选地，所述闪速存储器单元是Fowler-Nordheim隧效应细胞。

公开(公告)号：EP0530159B1

公开(公告)日：1997-07-02

申请号：EP92830458.3

申请日：1992-08-27

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Olivo, Marco

IPC: H03K17/22

CPC classification number: H03K17/223 ,  H03K2217/0036

公开(公告)号：EP0703667B1

公开(公告)日：1997-06-25

申请号：EP94830436.5

申请日：1994-09-16

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Diazzi, Claudio ,  Martignoni, Fabrizio ,  Tarantola, Mario

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03K17/161

公开(公告)号：EP0703666B1

公开(公告)日：1997-06-25

申请号：EP94830435.7

申请日：1994-09-16

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Diazzi, Claudio ,  Martignoni, Fabrizio ,  Tarantola, Mario

IPC: H03K17/687

CPC classification number: H03K3/356113 ,  H03K17/063 ,  H03K17/161 ,  H03K17/687

公开(公告)号：EP0287870B1

公开(公告)日：1997-06-25

申请号：EP88105164.3

申请日：1988-03-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Massironi, Angelo

IPC: H05K3/30

CPC classification number: H01L23/49548 ,  H01L2924/0002 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/09709 ,  H05K2201/10696 ,  H05K2201/10757 ,  H05K2201/10871 ,  H01L2924/00