公开(公告)号：KR1020030097442A

公开(公告)日：2003-12-31

申请号：KR1020020034815

申请日：2002-06-21

Applicant: 삼성전자주식회사

Inventor： 김성태 ,  김영선 ,  남갑진 ,  김기철 ,  임재순

IPC: H01L21/318

Abstract: PURPOSE: A method for fabricating a nitride layer of a semiconductor device is provided to reduce plasma damage to a material layer under the nitride layer by forming pre-activated nitrogen gas and by inducing the nitrogen gas to a nitridification chamber so that the nitrogen gas is activated to be a plasma state. CONSTITUTION: The material layer is formed on a semiconductor substrate. The semiconductor substrate with the material layer is induced to the nitridification chamber(S150). Nitrogen gas is induced to a pre-activation unit connected to the nitridification chamber to form pre-activated nitrogen gas(S155). The pre-activated nitrogen gas is induced to the nitridification chamber to form activated nitrogen gas(S160). The activated nitrogen gas reacts with the material layer to form a nitride layer on the material layer(S165).

Abstract translation: 目的：提供一种制造半导体器件的氮化物层的方法，通过形成预活化的氮气并通过将氮气引入氮化室来减少对氮化物层下面的材料层的等离子体损伤，使氮气为 激活成等离子体状态。 构成：材料层形成在半导体衬底上。 将具有材料层的半导体衬底引入氮化室（S150）。 氮气被诱导到与氮化室连接的预激活单元以形成预活化的氮气（S155）。 将预活化的氮气引入硝化室以形成活性氮气（S160）。 活性氮气与材料层反应，在材料层上形成氮化物层（S165）。

公开(公告)号：KR1020030090873A

公开(公告)日：2003-12-01

申请号：KR1020020028472

申请日：2002-05-22

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  이승환 ,  김영선

IPC: H01L21/31

Abstract: PURPOSE: A wafer processing apparatus is provided to efficiently form a mold oxide layer of a multilayer structure necessary for forming a cylindrical capacitor of a high integrated semiconductor memory device without being exposed to the atmosphere. CONSTITUTION: A cassette(114) into which a wafer(112) is loaded is positioned in a loadlock chamber(110). A vacuum-exhausted transfer chamber(120) has a robot arm(122) capable of loading and unloading the wafer. A plurality of vacuum processing chambers are connected to the transfer chamber through a gate valve. The first oxide layer is deposited in the first chamber(130). A heat treatment process is performed on the first oxide layer in the second chamber(140). The second oxide layer different from the first oxide layer is formed on the first oxide layer in the third chamber(150).

Abstract translation: 目的：提供晶片处理装置，以有效地形成形成高集成半导体存储器件的圆柱形电容器而不暴露于大气所需的多层结构的模制氧化物层。 构成：装载有晶片（112）的盒（114）位于负载锁定室（110）中。 真空排出的传送室（120）具有能够加载和卸载晶片的机器人手臂（122）。 多个真空处理室通过闸阀连接到传送室。 第一氧化物层沉积在第一室（130）中。 对第二室（140）中的第一氧化物层进行热处理工艺。 与第一氧化物层不同的第二氧化物层形成在第三室（150）的第一氧化物层上。

公开(公告)号：KR1020020043815A

公开(公告)日：2002-06-12

申请号：KR1020000072940

申请日：2000-12-04

Applicant: 삼성전자주식회사

Inventor： 이승환 ,  박기연 ,  임재순

IPC: H01L27/108

CPC classification number: H01L28/91 ,  H01L28/84

Abstract: PURPOSE: A method for fabricating a hemispherical grain capacitor is provided to prevent adjacent lower electrodes from being short-circuited, by preventing the lower electrodes from protruding over a mold insulation layer even if a part of the mold insulation layer is eliminated by the limit of etch selectivity when removing a planarizing insulation layer. CONSTITUTION: The mold insulation layer(140) having an opening in a region for a capacitor is formed on a substrate. Silicon of a uniform thickness is deposited on the mold insulation layer to form a lower electrode layer having a concave part. An insulation material is deposited on the lower electrode layer to fill the concave part so that the planarizing insulation layer(180') is formed. The planarizing insulation layer and the lower electrode layer are eliminated until the mold insulation layer is exposed so that a cylindrical lower electrode(165) is formed. A part of the upper portion of the lower electrode is removed to be lower than the surface of the planarizing insulation layer and the mold insulation layer. The planarizing insulation layer is removed to expose the concave part of the lower electrode. A hemispherical grain is formed on the surface of the concave part of the exposed lower electrode. A dielectric layer and an upper electrode are formed on the cylindrical lower electrode having the hemispherical grain.

Abstract translation: 目的：制造半球形晶粒电容器的方法是通过防止下电极在模具绝缘层上突出，以防止相邻的下电极短路，即使绝缘层的一部分被限制 去除平坦化绝缘层时的蚀刻选择性。 构成：在基板上形成具有用于电容器的区域中的开口的模具绝缘层（140）。 在模具绝缘层上沉积均匀厚度的硅以形成具有凹部的下电极层。 在下电极层上沉积绝缘材料以填充凹部，从而形成平坦化绝缘层（180'）。 除去平坦化绝缘层和下电极层，直到露出模具绝缘层，从而形成圆柱形下电极（165）。 除去下部电极的上部的一部分以使其低于平坦化绝缘层和模具绝缘层的表面。 去除平坦化绝缘层以露出下电极的凹部。 在露出的下电极的凹部的表面上形成半球状的晶粒。 在具有半球形颗粒的圆筒形下电极上形成电介质层和上电极。

公开(公告)号：KR1020010039874A

公开(公告)日：2001-05-15

申请号：KR1020000053415

申请日：2000-09-08

Applicant: 삼성전자주식회사

Inventor： 김영관 ,  박영욱 ,  임재순 ,  최성제 ,  이상인

IPC: C23C16/12

CPC classification number: C23C16/45553 ,  C07F5/063 ,  C23C16/403

Abstract: PURPOSE: A method for forming a thin film using an atomic layer deposition is provided to obtain a superior stoichiometric thin film by restraining the formation of undesirable impurities when using the atomic layer deposition. CONSTITUTION: The method comprises the steps of chemically adsorbing the first reactant on the substrate by infusing first reactant comprising elements consisting the thin film and ligands into a reaction chamber containing a substrate; removing the first reactant physically adsorbed by purging the reaction chamber with an inert gas; and forming an atomic layer unit of thin film by the chemical reaction of the elements consisting the thin film with the second reactant by infusing second reactant of which binding energy with the elements consisting the thin film is greater than the ligands into the reaction chamber and simultaneously removing the ligands without any side reactions. The method comprises the steps of chemically adsorbing the first reactant on the substrate by infusing first reactant into a substrate loaded reaction chamber (101); removing the physically adsorbed first reactant by purging the reaction chamber with an inert gas (103); forming an atomic layer unit of thin film by the chemical substitution of the first reactant with the second reactant by infusing second reactant into the reaction chamber (105); removing the physically adsorbed second reactant by purging the reaction chamber with an inert gas (107); and infusing third reactant for removing impurities and improving stoichiometry into the thin film formed reaction chamber.

Abstract translation: 目的：提供使用原子层沉积形成薄膜的方法，通过在使用原子层沉积时抑制不期望的杂质的形成来获得优异的化学计量薄膜。 构成：该方法包括以下步骤：通过将包含由薄膜和配体组成的元素的第一反应物注入到含有基底的反应室中来将基底上的第一反应物化学吸附; 通过用惰性气体清洗反应室来除去物理吸附的第一反应物; 并且通过将由薄膜构成的结合能与结合能量的第二反应物注入到反应室中的配体之间，通过由构成薄膜的元件与第二反应物的化学反应形成薄膜的原子层单元，同时 去除配体而没有任何副反应。 该方法包括以下步骤：通过将第一反应物注入基底负载的反应室（101）中来在基底上化学吸附第一反应物; 通过用惰性气体（103）吹扫反应室来除去物理吸附的第一反应物; 通过将第二反应物注入到反应室（105）中，通过第一反应物与第二反应物的化学取代形成薄膜的原子层单元; 通过用惰性气体（107）清洗反应室来除去物理吸附的第二反应物; 并且将第三反应物注入到去除薄膜形成的反应室中以除去杂质并改善化学计量。

公开(公告)号：KR101547313B1

公开(公告)日：2015-09-07

申请号：KR1020080117490

申请日：2008-11-25

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  조규호 ,  최재형 ,  김윤수

IPC: H01L21/316

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513

Abstract: 유전막을갖는반도체소자를제공한다. 이소자는기판및 기판상에배치되고, 도핑원자들로도핑된하프늄산화막을포함한다. 도핑원자의이온크기는하프늄원자의이온크기보다크고, 도핑된하프늄산화막은정방정계단위격자들을포함한다.

公开(公告)号：KR1020110072331A

公开(公告)日：2011-06-29

申请号：KR1020090129209

申请日：2009-12-22

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  김윤수 ,  최재형 ,  강상열 ,  정숙진

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L28/40 ,  C01G23/047 ,  C01G25/02 ,  C01P2002/72 ,  C01P2004/03 ,  C01P2006/40

Abstract: PURPOSE: A semiconductor device, a manufacturing method thereof, a semiconductor module including the same, an electronic circuit board, and an electronic system are provided to improve productivity by forming a semiconductor device with a capacitor including titanium oxide of rutile. CONSTITUTION: A lower vanadium dioxide layer(150) of rutile is formed on a bottom electrode. A titanium oxide layer(160) of rutile is formed on the lower vanadium dioxide layer. A top electrode(180) is formed on the titanium oxide layer. The bottom electrode includes vanadium. An upper vanadium dioxide layer of rutile is formed between the titanium oxide layer and the top electrode.

Abstract translation: 目的：提供一种半导体器件及其制造方法，包括该半导体器件的半导体模块，电子电路板和电子系统，以通过形成具有金红石氧化钛的电容器的半导体器件来提高生产率。 构成：在底部电极上形成金红石的较低二氧化钒层（150）。 在下层二氧化钒层上形成金红石的氧化钛层（160）。 顶部电极（180）形成在氧化钛层上。 底部电极包括钒。 在氧化钛层和顶部电极之间形成金红石的上层二氧化二钒层。

公开(公告)号：KR1020110008398A

公开(公告)日：2011-01-27

申请号：KR1020090065739

申请日：2009-07-20

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  김윤수 ,  김중현 ,  김완돈 ,  임재순 ,  강상열

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L23/5223 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53261 ,  H01L28/56 ,  H01L28/91 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A layer structure, a capacitor including the layer structure and a method of manufacturing the same are provided to improve the interference characteristics between a conductive film and a dielectric film by forming the conductive film and the dielectric film. CONSTITUTION: A conductive film(110) is comprised of a metal-nitride including vanadium(V), niobium(Nb) or alloy of them. A dielectric layer(120) is formed on the conductive film while is comprise of a high-k dielectric material. A metal-nitride has a cubic crystalline structure or a hexagonal crystalline structure. Electric charge is stored inside the dielectric layer between electrodes facing with each other.

Abstract translation: 目的：提供层结构，包括层结构的电容器及其制造方法，以通过形成导电膜和电介质膜来改善导电膜和电介质膜之间的干涉特性。 构成：导电膜（110）由包括钒（V），铌（Nb）或它们的合金的金属氮化物组成。 介电层（120）形成在导电膜上，同时包含高k电介质材料。 金属氮化物具有立方晶体结构或六方晶系结构。 在电极彼此面对的电介质层之间存储电荷。

公开(公告)号：KR1020080084434A

公开(公告)日：2008-09-19

申请号：KR1020070026153

申请日：2007-03-16

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  조규호 ,  김윤수 ,  이광희 ,  최재형 ,  임재순

IPC: H01L27/04 ,  H01L27/108

Abstract: A MIM(Metal-Insulator-Metal) capacitor and a method for fabricating the same are provided to improve the interface property and reduce the leakage current of the MIM capacitance by using an upper interface dielectric layer which is higher than a bulk dielectric layer in specific resistance. A MIM(Metal-Insulator-Metal) capacitor comprises a lower metal electrode(100), a lower interface dielectric layer(110), a bulk dielectric layer(120), an upper interface dielectric layer(130), and an upper metal electrode(140). The lower interface dielectric layer is formed on the lower metal electrode. The bulk dielectric layer is formed on the lower interface dielectric layer and made from material having more than 100 of permittivity. The upper interface dielectric layer is formed on the bulk dielectric layer. The upper metal electrode is formed on the upper interface dielectric layer. The lower interface dielectric layer, the bulk dielectric layer, and the upper interface dielectric layer have perovskite structure respectively. Both lower and upper interface dielectric layers are higher than the bulk dielectric layer in specific resistance.

Abstract translation: 提供MIM（金属 - 绝缘体 - 金属）电容器及其制造方法，以通过使用高于特定的体电介质层的上界面电介质层来改善MIM电容的界面性能并减小MIM电容的漏电流 抵抗性。 MIM（金属 - 绝缘体 - 金属）电容器包括下金属电极（100），下界面电介质层（110），体电介质层（120），上界面电介质层（130）和上金属电极 （140）。 下界面电介质层形成在下金属电极上。 体电介质层形成在下界面电介质层上并由具有大于100介电常数的材料制成。 上界面电介质层形成在体电介质层上。 上部金属电极形成在上部界面电介质层上。 下界面电介质层，体电介质层和上界面电介质层分别具有钙钛矿结构。 下界面和上界面电介质层都比电介质层的电阻率高。

公开(公告)号：KR1020060070010A

公开(公告)日：2006-06-23

申请号：KR1020040108627

申请日：2004-12-20

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  조규호 ,  임한진 ,  이진일 ,  김기철

IPC: H01L21/8247

CPC classification number: H01L27/0629 ,  H01L27/115 ,  H01L27/11521

Abstract: 박막 제조 방법 및 이를 이용한 게이트 구조물, 커패시터와 플래시 메모리 장치의 제조 방법에서, 챔버 내에 기판을 위치시킨 후, 지르코늄 전구체 물질과 티타늄 전구체 물질이 혼합된 반응 물질 및 상기 반응 물질을 산화시키기 위한 산화제를 상기 기판 상부로 제공한다. 그 결과, 상기 기판 상에는 지르코늄-티타늄-산화물을 함유하는 고체 물질로 이루어지는 박막이 형성된다. 그리고, 상기 박막을 게이트 구조물의 게이트 절연막, 커패시터의 유전막 또는 플래시 메모리 장치의 유전막 등에 용이하게 적용한다.

公开(公告)号：KR1020060017452A

公开(公告)日：2006-02-23

申请号：KR1020040092686

申请日：2004-11-12

Applicant: 삼성전자주식회사

Inventor： 이광희 ,  김진용 ,  정숙진 ,  조규호 ,  임한진 ,  이진일 ,  김기철 ,  임재순

IPC: H01L27/04

CPC classification number: H01L28/65 ,  H01L21/02244 ,  H01L21/02337 ,  H01L21/0234

Abstract: 엠아이엠 커패시터의 형성방법들 및 그에 의해 제조된 엠아이엠 커패시터들을 제공한다. 엠아이엠 커패시터를 형성하는 방법들은 반도체기판 상에 하부전극을 형성하는 것을 구비한다. 상기 하부전극 상에 하부 유전막을 형성하고, 상기 하부 유전막 상에 상부 유전막을 형성한다. 상기 하부 유전막은 상기 상부 유전막 보다 큰 에너지 밴드 갭을 갖는 유전막으로 형성한다. 상기 상부 유전막 상에 상부전극을 형성한다. 상기 상부전극은 상기 하부전극 보다 큰 일 함수를 갖는 금속막으로 형성한다.
엠아이엠 커패시터, 고유전막, 누설전류, 금속 전극