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公开(公告)号：KR101210616B1
公开(公告)日：2012-12-11
申请号：KR1020100134210
申请日：2010-12-24
Applicant: 전자부품연구원
CPC classification number: H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2224/18 , H01L2924/00012
Abstract: 다층반도체소자의제조방법은하부기판에금속핀을형성하고, 상부기판에금속핀의위치에대응하여구멍을형성한후에상부기판에형성된구멍에하부기판에형성된금속핀을삽입함으로써하부기판위에상부기판을적층한다. 다음, 상부기판과금속핀 사이의공간을유기물질로채워절연층을형성한후에금속핀과상부기판에형성된소자의적어도일부의절연층을제거하여연결부재를형성한다.
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公开(公告)号：KR1020110120668A
公开(公告)日：2011-11-04
申请号：KR1020100040180
申请日：2010-04-29
Applicant: 전자부품연구원
IPC: H01P1/213
CPC classification number: H01P1/213 , H01P1/20345 , H01P1/2084 , H03H7/463
Abstract: PURPOSE: A diplexer is provided to reduce a parasitic component by forming the circuit structure of capacitors, in which high pass filters are connected in a delta shape, and an inner pattern structure. CONSTITUTION: A branch node(N1) is connected to an antenna. The branch node receives a signal. A low pass filter(310) receives a received signal through the branch node. A low pass filter passes through a low band signal which is included in the received signal. A high pass filter(320) passes through a high band signal which is included in the received signal and a first, a second, and a third capacitor which are connected in a delta shape.
Abstract translation: 目的：提供双工器，通过形成高通滤波器以三角形形式连接的电容器的电路结构和内部图案结构来减少寄生成分。 构成：分支节点（N1）连接到天线。 分支节点接收信号。 低通滤波器（310）通过分支节点接收接收的信号。 低通滤波器通过包含在接收信号中的低频带信号。 高通滤波器（320）通过包含在接收信号中的高频带信号和连接成delta形状的第一，第二和第三电容器。
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公开(公告)号：KR101080035B1
公开(公告)日：2011-11-04
申请号：KR1020090082328
申请日：2009-09-02
Applicant: 전자부품연구원
Abstract: 스위치모듈을제조하는방법은 a) 동박상에반경화폴리머층을적층하는단계; b) 상기반경화폴리머층 상에스위치 IC 및하나이상의수동소자를실장하는단계; c) 상기반경화폴리머층 상의, 상기스위치 IC 및상기하나이상의수동소자사이에형성되는공간을반경화폴리머를채우는단계; d) 단계 c)에의해얻는결과물을라미네이트하는단계; e) 단계 d)에의해얻은결과물에서상기동박을제거하는단계; 및 f) 단계 e)에의해얻은기판의상부및 하부에회로패턴을형성하는단계를포함한다.
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公开(公告)号：KR1020110047781A
公开(公告)日：2011-05-09
申请号：KR1020090104542
申请日：2009-10-30
Applicant: 전자부품연구원
CPC classification number: H01L21/52
Abstract: PURPOSE: A semiconductor chip package method is provided to shorten the packaging time of a semiconductor chip by aligning and attaching a chip once through an exposure process using a dicing tape and a photomask. CONSTITUTION: A dicing tape(100) is attached to a wafer and the wafer is diced. The dicing tape is exposed through a photomask(300) including an exposure area to cover a diced chip area. A chip corresponding to the exposure area is attached to an attachment area by contacting the substrate with the dicing tape.
Abstract translation: 目的：提供一种半导体芯片封装方法，通过使用切割胶带和光掩模的曝光工艺对准和附接芯片来缩短半导体芯片的封装时间。 构成：将切割胶带（100）附接到晶片并切割晶片。 切割胶带通过包括曝光区域的光掩模（300）曝光以覆盖切片芯片区域。 通过使基板与切割带接触，将与曝光区域对应的芯片附着到安装区域。
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公开(公告)号：KR1020100128683A
公开(公告)日：2010-12-08
申请号：KR1020090047232
申请日：2009-05-29
Applicant: 전자부품연구원
CPC classification number: H03H9/64 , H03H9/02574 , H04B1/38 , H04B1/44 , H05K3/46
Abstract: PURPOSE: A front end module for wireless local area network(LAN) and a method for manufacturing the same are provided to reduce the height of the module by embedding components in the printed circuit board. CONSTITUTION: A front end module for wireless LAN(200) includes a power amplifier module(PAM) integrated circuit(IC)(103) for amplifying a system outputting signal and a receiving band passing filter(104) eliminating an unnecessary signal from a receiving terminal. The front end module for wireless LAN includes a transmitting low-band passing filter(101) and includes a switch IC(105) and a PAM matching terminal(102). The switch IC time-divisionally connects a transmitting signal and a receiving signal. The PAM matching terminal improves the signal property of a power amplifier.
Abstract translation: 目的：提供用于无线局域网（LAN）的前端模块及其制造方法，以通过将部件嵌入印刷电路板来降低模块的高度。 构成：用于无线LAN（200）的前端模块包括用于放大系统输出信号的功率放大器模块（PAM）集成电路（IC）（103）和接收频带通过滤波器（104），消除来自接收的不必要的信号 终奌站。 无线LAN的前端模块包括发送低通滤波器（101），并包括开关IC（105）和PAM匹配终端（102）。 开关IC分时连接发送信号和接收信号。 PAM匹配终端提高功率放大器的信号特性。
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Patent Agency Ranking
公开(公告)号：KR1020090124724A
公开(公告)日：2009-12-03
申请号：KR1020080051090
申请日：2008-05-30
Applicant: 전자부품연구원
Abstract: PURPOSE: A composite resin composition with low dielectric loss is provided to improve crosslinking property, heat resistance and fire retardant characteristic, and to ensure excellent dielectric properties such as low dielectric loss showing transmission characteristic suitable for a high frequency band. CONSTITUTION: A composite resin composition with low dielectric loss comprises a base resin containing poly(phenylene oxide), a crosslinking agent for imparting a crosslinking property to the base resin, an initiator, and an organic flame retardant in which at least 5 hydrogens are substituted with brome(Br), as a flame retardant which is not related to the cross-linking reaction.
Abstract translation: 目的：提供具有低介电损耗的复合树脂组合物，以提高交联性，耐热性和阻燃特性，并且确保优异的介电特性，例如低介电损耗，表现出适用于高频带的传输特性。 构成：具有低介电损耗的复合树脂组合物包括含有聚（苯醚）的基础树脂，赋予基础树脂交联性的交联剂，引发剂和至少5个氢被取代的有机阻燃剂 与溴化钡（Br），作为与交联反应无关的阻燃剂。
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公开(公告)号：KR100769455B1
公开(公告)日：2007-10-22
申请号：KR1020060072160
申请日：2006-07-31
IPC: H01C17/00
Abstract: A method for forming a built-in resistor by using a photo-sensitive resistive paste is provided to reduce a variation of a resistance of the photo-sensitive resistive paste by using a PSR(Photo Solder Resist) and a conductive filler. A pair of conductive units(111,112) are arranged to be apart from each other on a support unit(100). A photo-sensitive resistive paste(121) is applied on the support unit to enclose the conductive units. A mask is positioned at a region apart from an upper portion of the photo-sensitive resistive paste, and the photo-sensitive resistive paste is exposed by using the mask. A non-exposed photo-sensitive resistive paste is removed by using a developing solution. A non-removed photo-sensitive resistive paste is cured to form a resistive material. A protective film is formed on the support unit to enclose the resistive material and the conductive units. The photo-sensitive resistive paste is made of a conductive filler, a photo solder resist, a dispersing agent, and a solvent. A concentration of the conductive filler is between 7 and 15 w%.
Abstract translation: 提供了通过使用光敏电阻膏形成内置电阻器的方法，以通过使用PSR（光电抗蚀剂）和导电填料来减少光敏电阻膏的电阻的变化。 一对导电单元（111,112）被布置成在支撑单元（100）上彼此分开。 在支撑单元上施加光敏电阻膏（121）以包围导电单元。 掩模位于与感光电阻膏的上部隔开的区域，并且通过使用掩模曝光感光电阻膏。 通过使用显影液除去未曝光的感光电阻膏。 未去除的光敏电阻膏被固化以形成电阻材料。 在支撑单元上形成保护膜以包围电阻材料和导电单元。 光敏电阻膏由导电填料，光阻焊剂，分散剂和溶剂制成。 导电填料的浓度为7至15w％。
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公开(公告)号：KR100734234B1
公开(公告)日：2007-07-02
申请号：KR1020060048144
申请日：2006-05-29
Applicant: 전자부품연구원
IPC: H05K3/46
Abstract: A multilayer printed circuit board and a method for manufacturing the same are provided to have high resistance to an external impact by enclosing a circuit pattern with an insulation layer and to improve the yield and shorten a manufacturing time by integrally laminating laminated plates through thermal compression. A multilayer printed circuit board includes a first laminated plate, a second laminated plate. The first laminated plate has a first insulating layer(130), a first circuit pattern(115), a first via-hole(150), and a conductive material. The first circuit pattern(115) is laid on the first insulating layer(130). A lower part of the first circuit pattern(115) is exposed. The first via-hole(150) is formed on an upper part of the first circuit pattern(115) and penetrates the first insulating layer(130). The conductive material is filled in the first via-hole(150). A second circuit pattern is laid on a location corresponding to the first circuit pattern of a second insulating layer. An upper part of the second circuit pattern is exposed. A second via-hole is formed on a lower part of the second circuit pattern and penetrates the second insulating layer. A conductive material is filled in the second via hole. The second laminated plate is electrically connected to the first laminated plate when the conductive material filled in the first via-hole corresponds to the conductive material filled in the second via-hole.
Abstract translation: 提供了一种多层印刷电路板及其制造方法，其通过用绝缘层包围电路图案而具有高的抗外部冲击性，并且通过热压缩一体地层压层压板来提高成品率并缩短制造时间。 多层印刷电路板包括第一层压板，第二层压板。 第一层压板具有第一绝缘层（130），第一电路图案（115），第一通孔（150）和导电材料。 第一电路图案（115）铺设在第一绝缘层（130）上。 第一电路图案（115）的下部暴露。 第一通孔（150）形成在第一电路图案（115）的上部并且穿透第一绝缘层（130）。 导电材料填充在第一通孔（150）中。 第二电路图案设置在对应于第二绝缘层的第一电路图案的位置上。 第二电路图案的上部被暴露。 第二通孔形成在第二电路图案的下部并穿透第二绝缘层。 导电材料填充在第二通孔中。 当填充在第一通孔中的导电材料对应于填充在第二通孔中的导电材料时，第二层压板电连接到第一层压板。
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公开(公告)号：KR100723270B1
公开(公告)日：2007-05-30
申请号：KR1020050122239
申请日：2005-12-13
Applicant: 전자부품연구원
IPC: H05K3/46
Abstract: 본 발명은 다층 인쇄회로기판 제조방법에 관한 것으로, 복수의 금속 박막의 일면에 각각 제1보호 필름을 형성하는 단계; 상기 각 금속 박막의 타면에 도전성 범프(Bump)를 형성하는 단계; 상기 각 금속 박막의 타면에, 일면에 제2보호 필름이 형성된 절연층을 적층하여 복수의 적층판을 형성하는 단계; 레이저를 이용하여 상기 각 적층판의 도전성 범프 위에 형성된 절연층 및 제2보호 필름을 제거하여, 도전성 범프를 노출시키는 단계; 상기 각 적층판의 제2보호 필름을 제거하는 단계; 상기 각 적층판의 제1보호 필름을 제거하고, 금속 박막을 식각하여, 각 적층판에 회로 패턴을 형성하는 단계; 및 상기 각 적층판을 압착하는 단계를 포함하여 이루어진다.
본 발명은 이러한 특징에 의해, 범프의 저항을 낮추어 다층 인쇄회로기판의 발열을 감소시킬 수 있으며, 드릴링에 의한 먼지가 발생하지 않는다.
다층 인쇄회로기판, 도전성 범프Abstract translation: 本发明涉及一种制造多层印刷电路板的方法，包括：在多个金属薄膜的一个表面上形成第一保护膜; 在每个金属薄膜的另一个表面上形成导电凸块; 通过在每个金属薄膜的另一个表面上层压具有第二保护膜的绝缘层在其一个表面上形成多个层压板; 使用激光去除形成在各个层压板的导电凸块上的绝缘层和第二保护膜以暴露导电凸块; 去除每个层压板的第二保护膜; 去除每个叠层板的第一保护膜，并蚀刻金属薄膜以在每个叠层板上形成电路图案; 并按下每个层压板。
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公开(公告)号：KR101607259B1
公开(公告)日：2016-03-29
申请号：KR1020140187007
申请日：2014-12-23
Applicant: 전자부품연구원
IPC: H01L27/108 , H01L21/8242
CPC classification number: H01L27/108
Abstract: 본발명은수동소자및 그제조방법에관한것이다. 본발명에 MIM(Metal Insulator Metal) 커패시터는기판의일면상에형성된커패시터박막패턴, 커패시터박막패턴이형성된기판을식각하여형성된트렌치(trench), 트렌치를충진하면서기판상에형성되어있으며커패시터를구성하는금속층들을노출시키는커패시터용배선홀들이형성되어있는절연층및 IM 커패시터용배선홀들에도전성물질을충진하여형성된커패시터전극배선을포함하고, 기판의타면은트렌치에형성된절연층이노출되도록연마되어있는것을특징으로한다. 본발명에따르면, 기판의타면즉, 수동소자가형성되는기판의일면과대향하는반대면이연마되어트렌치에형성된절연층이노출된구조를갖기때문에, 인접단위소자로의전기적누설의통로를원천적으로차단하여전기적손실을차단할수 있고, 이에따라, 최종제품인수동소자의고주파영역에서의전기적특성이크게향상되는효과가있다.
Abstract translation: 无源器件及其制造方法技术领域本发明涉及无源器件及其制造方法。 本发明的金属绝缘体金属（MIM）电容器包括：形成在基板的一个平面上的电容器薄膜图案; 通过蚀刻形成有电容器薄膜图案的基板而形成的沟槽; 绝缘层，其在填充沟槽的同时形成在衬底上，并且具有用于暴露构成电容器的金属层的电容器的线槽; 以及电容电极线，其通过将导电材料填充到用于IM电容器的线槽中而形成。 抛光衬底的另一个平面，使得形成在沟槽上的绝缘层可以被暴露。 根据本发明，由于形成在作为与被动元件形成的基板的一个平面相对的基板的另一平面的沟槽中的绝缘层具有绝缘层露出的结构， 该装置可以通过基本上阻挡泄漏到相邻单元装置的电流而阻断电气损耗，因此可以改善作为最终产品的无源装置的高频区域中的电气特性。
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