公开(公告)号：WO1996038917A1

公开(公告)日：1996-12-05

申请号：PCT/US1996004612

申请日：1996-04-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  AGRAWAL, Om, P. ,  SHARPE-GEISLER, Bradley, A. ,  SCHMITZ, Nicholas, A. ,  MOYER, Bryon, I.

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17704

Abstract: A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchical level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.

Abstract translation: 一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。 层次结构的最低层次与所有更高层次是独立的。 类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。 第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。 第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三层级信号路径利用第三级，第二级和第一层次级资源。 第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。

公开(公告)号：WO1996033575A1

公开(公告)日：1996-10-24

申请号：PCT/US1996005305

申请日：1996-04-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TUCKER, Michael, R. ,  STRONGIN, Geoffrey, S. ,  YI, Liu

IPC: H04N07/50

CPC classification number: H04N19/433 ,  H04N19/423 ,  H04N19/61

Abstract: A video decoding system that selectively arranges video information within a memory to correspond to macroblocks of video information. Such a system advantageously increases the efficiency of processing video information when decoding compressed video information.

Abstract translation: 一种视频解码系统，其选择性地将视频信息布置在存储器内以对应于视频信息的宏块。 这样的系统有利地提高了解压缩视频信息时处理视频信息的效率。

公开(公告)号：WO1996033558A1

公开(公告)日：1996-10-24

申请号：PCT/US1996005414

申请日：1996-04-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TUCKER, Michael, R. ,  STRONGIN, Geoffrey, S. ,  YI, Liu

IPC: H03M07/42

CPC classification number: H03M7/425 ,  H04N19/13 ,  H04N19/45 ,  H04N19/60 ,  H04N19/61 ,  H04N19/91

Abstract: A method and apparatus for decoding variable length code (VLC) data employ a hybrid technique of parsing short-length VLC codes using a binary tree or binary search procedure and parsing longer VLC codes using a table lookup procedure. This technique includes the steps of accessing a plurality of bits of coded bitstream data, bit testing a preselected number N first bits of the plurality of bitstream bits and determining whether the N first bits include a complete VLC code. If the N first bits include a complete VLC code, a VLC code is decoded in accordance with a result of the bit testing step. If the N first bits do not include a complete VLC code, a VLC code is decoded from a lookup table to a table element addressed by the bits of coded bitstream data.

Abstract translation: 用于解码可变长度码（VLC）数据的方法和装置采用使用二叉树或二进制搜索过程解析短长度VLC码并使用表查找过程解析较长VLC码的混合技术。 该技术包括以下步骤：访问编码比特流数据的多个比特，对多个比特流比特中的预先选择的N个第一比特进行比特测试，并确定N个第一比特是否包括完整的VLC码。 如果N个第一比特包括完整的VLC码，则根据比特测试步骤的结果对VLC码进行解码。 如果N个第一比特不包括完整的VLC码，VLC码将从查找表解码为由编码比特流数据的比特寻址的表格元素。

公开(公告)号：WO1996033496A1

公开(公告)日：1996-10-24

申请号：PCT/US1996004124

申请日：1996-03-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHARPE-GEISLER, Bradley, A.

IPC: G11C05/14

CPC classification number: G11C5/147 ,  G05F3/247

Abstract: A voltage reference for a CMOS memory cell having PMOS and NMOS transistors with a common floating gate. The reference provides a more stable voltage than voltage supplied from the Vcc pin of a chip. In one embodiment, the reference includes PMOS and NMOS transistors with a common floating gate connected to their drains. A weak current source supplies current to the source of the PMOS transistor of the reference so that voltage at the source of the PMOS transistor of the reference equals the magnitude of the sum of threshold voltages (Vtn + Vtp) of the NMOS and PMOS transistors of the reference. The voltage at the source of the PMOS transistor of the reference is provided as a reference to the source of the PMOS transistor of the CMOS memory cell. To assure zero power operation in subsequent cells following CMOS memory cells utilizing such a reference, cell implants are utilized in the CMOS memory cells and the reference to assure Vtn + Vtp is greater than or equal Vcc, and voltage to the reference is boosted above Vcc.

Abstract translation: 具有具有公共浮动栅极的PMOS和NMOS晶体管的CMOS存储单元的参考电压。 该参考电压提供比由芯片的Vcc引脚提供的电压更稳定的电压。 在一个实施例中，该参考包括PMOS和NMOS晶体管，其公共浮栅连接到它们的漏极。 弱电流源将电流提供给参考的PMOS晶体管的源极，使得基准PMOS晶体管的源极处的电压等于NMOS和PMOS晶体管的阈值电压（Vtn + Vtp）之和的大小， 参考。 提供了参考的PMOS晶体管的源极处的电压作为对CMOS存储器单元的PMOS晶体管的源极的参考。 为了保证在使用这种参考的CMOS存储器单元之后的后续单元中的零功率操作，在CMOS存储器单元中使用单元注入，并且参考以确保Vtn + Vtp大于或等于Vcc，并且参考电压升高到高于Vcc 。

公开(公告)号：WO1996027970A1

公开(公告)日：1996-09-12

申请号：PCT/US1996002835

申请日：1996-03-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ZHOU, Yan

IPC: H04M03/00

CPC classification number: H04M19/005 ,  H04M3/005

Abstract: DC level control for an electronic telephone line card which filters the DC component from the input audio signal, determines the gain setting of the transmit path, develops a DC adjust voltage opposite to that of the DC shift component and subtracts the DC adjust voltage to the input voltage to cancel the DC shift component. A quantized, discontinuous feedback path is implemented to respond only to DC shifts so the AC operation remains substantially unaffected. Such discontinuous feedback eliminates stability and impedance matching problems introduced with continuous feedback solutions. A DC control circuit according to the present invention includes a low pass filter for detecting DC shifts, a quantizer for asserting an incremental signal, a threshold detector for activating adjustment functions, and an accumulator for developing the DC adjust voltage by incremental steps. A long term low pass filter and reset circuit resets the accumulator to cancel residual DC adjust voltages which might otherwise reduce the dynamic range of the telephone line transmit path.

Abstract translation: 对来自输入音频信号对DC分量进行滤波的电子电话线卡的DC电平控制，确定发送路径的增益设定，产生与DC移位分量相反的DC调整电压，并将DC调整电压减去为 输入电压来取消直流偏移分量。 实现量化的不连续反馈路径以仅响应于DC偏移，使得AC操作基本上不受影响。 这种不连续的反馈消除了连续反馈解决方案引入的稳定性和阻抗匹配问题。 根据本发明的直流控制电路包括用于检测直流偏移的低通滤波器，用于断言增量信号的量化器，用于启动调节功能的阈值检测器，以及用于通过增量步长产生直流调节电压的累加器。 长期的低通滤波器和复位电路使累加器复位以消除残留的DC调整电压，否则可能会降低电话线路传输路径的动态范围。

公开(公告)号：WO1996024467A1

公开(公告)日：1996-08-15

申请号：PCT/US1996000152

申请日：1996-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LEE, Dawn, M. ,  VENKATKRISHNAN, Subramanian

IPC: B24B37/04

CPC classification number: B24B37/30

Abstract: Uniform planarization of a patterned semiconductor wafer is effected with a chemical-mechanical polishing apparatus containing a base plate comprising a convex surface portion.

Abstract translation: 图案化半导体晶片的均匀平坦化由含有包括凸面部分的基板的化学机械抛光装置进行。

公开(公告)号：WO1996024155A1

公开(公告)日：1996-08-08

申请号：PCT/US1996000572

申请日：1996-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KRIVOKAPIC, Zoran ,  BANG, David, S.

IPC: H01J37/34

CPC classification number: H01J37/3447 ,  H01J37/34

Abstract: A collimator system for use in PVD sputtering of semiconductor wafers having multiple tiers provided between a target and wafer substrate. The collimator system prevents target atoms from contacting the wafer at substantially oblique angles, thereby providing good step coverage uniformity over the surface of the wafer. Additionally, the presence of more than one tier prevents localized build-up of target atoms that occurs in conventional single tier collimators, thereby providing good flat coverage uniformity over the surface of the wafer.

Abstract translation: 一种用于半导体晶片的PVD溅射的准直器系统，其具有设置在靶和晶片衬底之间的多层。 准直器系统防止目标原子以基本倾斜的角度接触晶片，从而在晶片的表面上提供良好的阶梯覆盖均匀性。 另外，存在多于一层防止在常规单层准直仪中发生的目标原子的局部积累，从而在晶片的表面上提供良好的平坦覆盖均匀性。

公开(公告)号：WO1996021302A1

公开(公告)日：1996-07-11

申请号：PCT/US1995015259

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian

IPC: H04L12/46

CPC classification number: H04L12/46 ,  H04L12/18 ,  H04L12/44 ,  H04L45/7453 ,  H04L63/10

Abstract: In a repeater (10) having multiple ports (40) and receiving at a source port a data packet containing a received address, an address mapping system including a content addressable memory (CAM) with address registers containing stored addresses, and an address mapping matrix (100) coupled to said CAM, for perfectly mapping any of the address registers to any of the ports. According to one aspect of the invention, it operates in a repeater having an address compare and disrupt security system. The preferred embodiment of the present invention includes a content addressable memory having address registers containing stored individual and multicast addresses associated with each repeater port, and an address mapping matrix including a disrupt enable circuit (120) associated with each port, for enabling the disruption of the data packet at that port when the received destination address does not match the associated stored addresses, and for disabling the disruption of the data packet at that port when the received destination address matches the stored address in a particular register and that particular register is mapped to that port via an address mapping register (110).

Abstract translation: 在具有多个端口（40）并且在源端口接收包含接收到的地址的数据分组的中继器（10）中，包括具有包含存储的地址的地址寄存器的内容可寻址存储器（CAM）的地址映射系统以及地址映射矩阵 （100），用于将任何地址寄存器完美地映射到任何端口。 根据本发明的一个方面，其操作在具有地址比较和中断安全系统的中继器中。 本发明的优选实施例包括内容可寻址存储器，其具有包含与每个中继器端口相关联的存储的单独和多播地址的地址寄存器，以及包括与每个端口相关联的中断使能电路（120）的地址映射矩阵， 当接收到的目的地地址与相关联的存储地址不匹配时，该端口处的数据分组，以及当接收到的目的地地址与特定寄存器中存储的地址匹配并且该特定寄存器被映射时禁止在该端口处的数据分组的中断 经由地址映射寄存器（110）发送到该端口。

公开(公告)号：WO1996019753A1

公开(公告)日：1996-06-27

申请号：PCT/US1995014302

申请日：1995-11-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GUPTA, Subhash ,  LYONS, Chris, F.

IPC: G03F07/36

CPC classification number: G03F7/36

Abstract: A photolithographic substrate mask patterning method which enables the reduction of changes in critical dimensions which occur in prior art etching of organic photoresist and the underlying organic i-line bottom anti-reflection layer (BARL) on a non-planar substrate. Based on the minor difference in the total carbon and oxygen content between the organic photoresist and the organic BARL, a differential in polarization is achieved using a pure N2 plasma for ion etching at certain selected conditions and a selectivity is achieved between the etch rate of the organic photoresist as compared to the etch rate of the organic BARL.

Abstract translation: 一种光刻基板掩模图案化方法，其能够减少在非平面基板上有机光致抗蚀剂和下面的有机i线底抗反射层（BARL）的现有技术蚀刻中出现的临界尺寸变化。 基于有机光致抗蚀剂和有机BARL之间的总碳和氧含量的微小差异，在某些选定条件下使用纯N 2等离子体进行离子蚀刻来实现极化差异，并且在 有机光致抗蚀剂与有机BARL的蚀刻速率相比。

公开(公告)号：WO1996017380A1

公开(公告)日：1996-06-06

申请号：PCT/US1995014447

申请日：1995-10-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HOLZWORTH, Raymond

IPC: H01L21/762

CPC classification number: H01L21/823807 ,  H01L21/76218

Abstract: A method and apparatus provides an integrated circuit device that allows for a high field threshold voltage by minimizing the parasitic transistors located therein. The integrated circuit includes a well region, a source/drain region, a nitride layer and a first oxide layer coupled to the well region. The system masks and etches a nitride layer and then provides a field implant region in the well area. Thereafter, it etches the nitride again where the field implant region is moved away from the source/drain region. In so doing, the field implant region is spaced away from the source/drain region of the device and therefore the breakdown voltage of the device is effectively increased.

Abstract translation: 一种方法和装置提供一种通过使位于其中的寄生晶体管最小化来允许高场阈值电压的集成电路器件。 集成电路包括阱区，源极/漏极区，氮化物层和耦合到阱区的第一氧化物层。 该系统掩盖和蚀刻氮化物层，然后在阱区域中提供场注入区域。 此后，其再次蚀刻氮化物，其中场注入区域远离源极/漏极区域移动。 在这样做时，场注入区域与器件的源极/漏极区域间隔开，因此器件的击穿电压被有效地提高。