Abstract:
A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchical level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.
Abstract:
A video decoding system that selectively arranges video information within a memory to correspond to macroblocks of video information. Such a system advantageously increases the efficiency of processing video information when decoding compressed video information.
Abstract:
A method and apparatus for decoding variable length code (VLC) data employ a hybrid technique of parsing short-length VLC codes using a binary tree or binary search procedure and parsing longer VLC codes using a table lookup procedure. This technique includes the steps of accessing a plurality of bits of coded bitstream data, bit testing a preselected number N first bits of the plurality of bitstream bits and determining whether the N first bits include a complete VLC code. If the N first bits include a complete VLC code, a VLC code is decoded in accordance with a result of the bit testing step. If the N first bits do not include a complete VLC code, a VLC code is decoded from a lookup table to a table element addressed by the bits of coded bitstream data.
Abstract:
A voltage reference for a CMOS memory cell having PMOS and NMOS transistors with a common floating gate. The reference provides a more stable voltage than voltage supplied from the Vcc pin of a chip. In one embodiment, the reference includes PMOS and NMOS transistors with a common floating gate connected to their drains. A weak current source supplies current to the source of the PMOS transistor of the reference so that voltage at the source of the PMOS transistor of the reference equals the magnitude of the sum of threshold voltages (Vtn + Vtp) of the NMOS and PMOS transistors of the reference. The voltage at the source of the PMOS transistor of the reference is provided as a reference to the source of the PMOS transistor of the CMOS memory cell. To assure zero power operation in subsequent cells following CMOS memory cells utilizing such a reference, cell implants are utilized in the CMOS memory cells and the reference to assure Vtn + Vtp is greater than or equal Vcc, and voltage to the reference is boosted above Vcc.
Abstract:
DC level control for an electronic telephone line card which filters the DC component from the input audio signal, determines the gain setting of the transmit path, develops a DC adjust voltage opposite to that of the DC shift component and subtracts the DC adjust voltage to the input voltage to cancel the DC shift component. A quantized, discontinuous feedback path is implemented to respond only to DC shifts so the AC operation remains substantially unaffected. Such discontinuous feedback eliminates stability and impedance matching problems introduced with continuous feedback solutions. A DC control circuit according to the present invention includes a low pass filter for detecting DC shifts, a quantizer for asserting an incremental signal, a threshold detector for activating adjustment functions, and an accumulator for developing the DC adjust voltage by incremental steps. A long term low pass filter and reset circuit resets the accumulator to cancel residual DC adjust voltages which might otherwise reduce the dynamic range of the telephone line transmit path.
Abstract:
Uniform planarization of a patterned semiconductor wafer is effected with a chemical-mechanical polishing apparatus containing a base plate comprising a convex surface portion.
Abstract:
A collimator system for use in PVD sputtering of semiconductor wafers having multiple tiers provided between a target and wafer substrate. The collimator system prevents target atoms from contacting the wafer at substantially oblique angles, thereby providing good step coverage uniformity over the surface of the wafer. Additionally, the presence of more than one tier prevents localized build-up of target atoms that occurs in conventional single tier collimators, thereby providing good flat coverage uniformity over the surface of the wafer.
Abstract:
In a repeater (10) having multiple ports (40) and receiving at a source port a data packet containing a received address, an address mapping system including a content addressable memory (CAM) with address registers containing stored addresses, and an address mapping matrix (100) coupled to said CAM, for perfectly mapping any of the address registers to any of the ports. According to one aspect of the invention, it operates in a repeater having an address compare and disrupt security system. The preferred embodiment of the present invention includes a content addressable memory having address registers containing stored individual and multicast addresses associated with each repeater port, and an address mapping matrix including a disrupt enable circuit (120) associated with each port, for enabling the disruption of the data packet at that port when the received destination address does not match the associated stored addresses, and for disabling the disruption of the data packet at that port when the received destination address matches the stored address in a particular register and that particular register is mapped to that port via an address mapping register (110).
Abstract:
A photolithographic substrate mask patterning method which enables the reduction of changes in critical dimensions which occur in prior art etching of organic photoresist and the underlying organic i-line bottom anti-reflection layer (BARL) on a non-planar substrate. Based on the minor difference in the total carbon and oxygen content between the organic photoresist and the organic BARL, a differential in polarization is achieved using a pure N2 plasma for ion etching at certain selected conditions and a selectivity is achieved between the etch rate of the organic photoresist as compared to the etch rate of the organic BARL.
Abstract:
A method and apparatus provides an integrated circuit device that allows for a high field threshold voltage by minimizing the parasitic transistors located therein. The integrated circuit includes a well region, a source/drain region, a nitride layer and a first oxide layer coupled to the well region. The system masks and etches a nitride layer and then provides a field implant region in the well area. Thereafter, it etches the nitride again where the field implant region is moved away from the source/drain region. In so doing, the field implant region is spaced away from the source/drain region of the device and therefore the breakdown voltage of the device is effectively increased.