公开(公告)号：ES2359893T3

公开(公告)日：2011-05-27

申请号：ES05108507

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08

Abstract: Un método para borrar elementos de memorias intermedias de traducción de direcciones en un sistema informático (300), comprendiendo el sistema informático una o más tablas de traducción de direcciones que facilitan información de traducción para traducir direcciones virtuales a las direcciones de la memoria, cada elemento de memoria intermedia de traducción de direcciones llevando dinámicamente en memoria caché información de traducción de direcciones, comprendiendo el método los pasos de: determinar a partir de un código de operación de una instrucción ejecutable por máquina que tiene que ser ejecutada que la instrucción está configurada para iniciar la ejecución de una operación de borrado; ejecutar la instrucción, caracterizado este paso de ejecutar porque comprende los pasos de: basándose en la primera dirección del origen de la tabla de traducción de direcciones de una primera tabla de traducción, limpiar (502) selectivamente uno o más primeros elementos de la memoria intermedia de traducción de direcciones de la memoria intermedia de traducción de direcciones, ese o más de los primeros elementos asociados con la primera dirección (624) de origen de la tabla de traducción, caracterizado porque la primera dirección del origen de la tabla de traducción es una cualquiera de entre una dirección del origen de la tabla de regiones y una dirección (624) del origen de la tabla de segmentos.

公开(公告)号：SI1653343T1

公开(公告)日：2011-01-31

申请号：SI200431564

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10

公开(公告)号：PL1701269T3

公开(公告)日：2009-10-30

申请号：PL06116358

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08

公开(公告)号：AT430963T

公开(公告)日：2009-05-15

申请号：AT06116358

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：DK1588267T3

公开(公告)日：2008-05-13

申请号：DK04731399

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：ES2297417T3

公开(公告)日：2008-05-01

申请号：ES04731399

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: Un método para borrar memorias intermedias de traducción de direcciones e invalidar una gama de elementos de una tabla de traducción de direcciones de almacenamiento asociadas en un sistema informático, comprendiendo el sistema informático una o más unidades centrales de proceso en comunicación con un almacenamiento principal, teniendo las unidades centrales de proceso unas memorias intermedias de traducción de direcciones, teniendo además la memoria intermedia de traducción de direcciones elementos de memoria intermedia de traducción de direcciones que mantienen la información de traducción de direcciones, teniendo el sistema informático tablas de páginas y otras tablas de traducción de direcciones para traducir las direcciones del almacenamiento principal virtual de una unidad central de proceso de una o más unidades de proceso, en direcciones del almacenamiento principal del sistema informático, comprendiendo las tablas de traducción de direcciones cualquiera de los siguientes: una o mástablas de segmentos, una o más tablas de segmentos y una o más tablas de la primera región, una o más tablas de segmentos y una o más tablas de la primera región y una o más tablas de la segunda región o una o más tablas de segmentos y una o más tablas de la primera región y una o más tablas de la segunda región y una o más tablas de la tercera región, donde un elemento de una tabla de segmentos comprende un origen de la tabla de páginas; estando caracterizado el método porque comprende los pasos de: extraer una instrucción multifunción (600) de ordenador de un Elemento de Tabla de Traducción Dinámica de Direcciones de Invalidación (IDTE), comprendiendo la instrucción multifunción IDTE un campo (602) de código de operación que tiene un valor del campo del código de operación que identifica la instrucción como una instrucción IDTE multifunción, siendo la instrucción IDTE multifunción para realizar una primera función o bien una segunda función, comprendiendo la primera función una operaciónde invalidación y borrado, y comprendiendo la segunda función una operación de borrado y no una operación de invalidación; ejecutar la instrucción IDTE multifunción realizando los pasos de: cuando la función de la instrucción IDTE multifunción extraída consiste en la operación de invalidación y borrado, realizar los pasos 1) y 2): 1) invalidar (404) una gama predeterminada de uno o más elementos de tabla de traducción de direcciones, de una tabla de traducción de direcciones, comenzando en un lugar predeterminado de un elemento de la tabla de direcciones; y 2) borrar (505), (508) memorias intermedias de traducción de direcciones de elementos de memorias intermedias de traducción de direcciones asociados con el uno o más elementos invalidados de la tabla de traducción de direcciones; cuando la función de la instrucción IDTE multifunción extraída consiste solamente en una operación de borrado, realizar el paso de: borrar memorias intermedias de traducción de direcciones de elementos de memorias intermedias de traducción de direcciones asociados con el uno o más elementos de la tabla de traducción de direcciones, comprendiendo el uno o más elementos de la tabla de traducción de direcciones una gama predeterminada de uno o más elementos de tabla de traducción de direcciones, de una tabla de traducción de direcciones, comenzando en un lugar predeterminado de un elemento de la tabla de traducción de direcciones.

公开(公告)号：DE602004011018D1

公开(公告)日：2008-02-07

申请号：DE602004011018

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：GB2414841B

公开(公告)日：2006-07-05

申请号：GB0518901

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY J ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F12/10

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：DE19929051C2

公开(公告)日：2001-10-04

申请号：DE19929051

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  LAUB OLIVER ,  PFEFFER ERWIN

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/38 ,  G06F9/32 ,  G06F9/318

Abstract: A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

公开(公告)号：DE10002120A1

公开(公告)日：2000-11-02

申请号：DE10002120

申请日：2000-01-20

Applicant: IBM

Inventor： GAERTNER UTE ,  PFEFFER ERWIN ,  SCHELM KERSTIN ,  MACDOUGALL JOHN

IPC: G06F12/1027 ,  G06F12/10

Abstract: The buffer storage arrangement has two dividing/partial units (82,84). The first one is a converting buffer (82) for certain higher address converting planes and the second a converting buffer (84) for certain lower address converting planes. The second unit (84) is arranged in such a way that is stores special converting cache (TLB) index address data of the higher unit (82) as a data marker flag in the TLB structure of the lower plane. The first converting buffer (TLB1) is a peak level buffer storage and a second (TLB2) is a second level address converting memory. It is arranged in such a way that it makes available this address data in case of a missing address in the first buffer storage and the second TLB2 is arranged so that it has at least two dividing/partial units (81,82,83,84), and LRU data is provided in both dividing/partial units (81,82,83,84). An Independent claim is also included for A Method for the operation of an address converting buffer arrangement.