公开(公告)号：DE102008034503A1

公开(公告)日：2009-02-05

申请号：DE102008034503

申请日：2008-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALLERS WOLF ,  BOLLU MICHAEL ,  NIRSCHL THOMAS ,  OTTERSTEDT JAN ,  PETERS CHRISTIAN ,  SOMMER MICHAEL BERNHARD

IPC: G11C13/02

Abstract: A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

公开(公告)号：DE102008028934A1

公开(公告)日：2009-01-02

申请号：DE102008028934

申请日：2008-06-18

Applicant: INFINEON TECHNOLOGIES AG ,  QIMONDA AG

Inventor： PHILIPP JAN BORIS ,  NIRSCHL THOMAS ,  HAPP THOMAS

IPC: H01L27/24 ,  G11C13/02 ,  H01L43/08

Abstract: An integrated circuit includes a diode including a first polarity region and a second polarity region. The second polarity region contacts a bottom and sidewalls of the first polarity region. The integrated circuit includes a first electrode coupled to the diode, a second electrode, and resistivity changing material between the first electrode and the second electrode.

公开(公告)号：DE102008017282A1

公开(公告)日：2008-10-30

申请号：DE102008017282

申请日：2008-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS

IPC: H01L27/24

公开(公告)号：DE102005048711A1

公开(公告)日：2007-04-26

申请号：DE102005048711

申请日：2005-10-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIRSCHL THOMAS ,  HENZLER STEPHAN ,  SCHMITT-LANDSIEDEL DORIS

IPC: G11C11/412

Abstract: Memory cell (10) comprises tunneling field effect transistors (TFETs). An independent claim is also included for a method for evaluating information stored in a memory cell.

公开(公告)号：DE102004056459B4

公开(公告)日：2007-01-18

申请号：DE102004056459

申请日：2004-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OSTERMAYR MARTIN ,  NIRSCHL THOMAS

IPC: G11C17/10 ,  G11C17/12

Abstract: The ROM cell of ROM memory provides first given potential (VDD) or second given potential (GND) in the accessed state at cell output depending on programming condition. The signal output of the control element (N-MOS) is connected with the cell output. The control element has a control input, which is fed with control signal. Independent claims are also included for the following: (A) ROM memory with arrangement of ROM cells; and (B) Programming the ROM cell.

公开(公告)号：DE102005029493A1

公开(公告)日：2006-02-23

申请号：DE102005029493

申请日：2005-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUEFER KLAUS ,  SHUM DANNY PAK-CHUM

IPC: G11C16/04 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/861

Abstract: A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

公开(公告)号：DE102004004584A1

公开(公告)日：2005-08-25

申请号：DE102004004584

申请日：2004-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLBRICH ALEXANDER ,  OSTERMAYR MARTIN ,  NIRSCHL THOMAS

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.