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    63.
    发明专利
    未知

    公开(公告)号：DE69829852T2

    公开(公告)日：2006-03-02

    申请号：DE69829852

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO ,  MASINI MARCO

    IPC: H03F3/217

    Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output, comprises two identical amplifying modules (1, 2), one (1) for the amplifying channel relative to the direct or positive PWM output (Vo-If+) and the other (2) for the amplifying channel relative to the inverted or negative PWM output (Vo-If+). Each modules includes a switching output operational amplifier (O1), having a voltage mode noninverting input (In+), a current mode inverting input (In-) and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform, a logic inverter or a cascade of logic inverters (C1) coupled in cascade to the output of the integrator (O1, LOOP FILTER) and outputting a logic PWM signal, an output power stage (P1) converting the logic PWM signal output by said inverter or cascade of logic inverters (C1) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor (Rf) connecting the output of power stage (P1) to the inverting input (In-) of said operational amplifier (O1).

    64.
    发明专利
    未知

    公开(公告)号：DE69922961T2

    公开(公告)日：2005-12-22

    申请号：DE69922961

    申请日：1999-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

    IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

    Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.

    65.
    发明专利
    未知

    公开(公告)号：DE69922961D1

    公开(公告)日：2005-02-03

    申请号：DE69922961

    申请日：1999-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

    IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

    Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.

    66.
    发明专利
    未知

    公开(公告)号：IT1313380B1

    公开(公告)日：2002-07-23

    申请号：ITVA990003

    申请日：1999-01-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  RANIERI DANILO

    IPC: H03F3/21 ,  H03F3/217

    Abstract: A switching output power stage, including a power switching device for the supply line and a complementary power switching device for the ground rail driven in phase opposition by a pulse width modulated (PWM) drive signal, is provided with sensors detecting a substantial turn-off state of each of the two power switching devices and generating a pair of logic signals. A combinatory logic circuit combines the drive signal and the pair of logic signals and generates a pair of driving signals of opposite phase for the respective power switching devices. The switching to a turn-on state of any of the two power devices is enabled upon verifying a substantially attained turn-off state by the device complementary to the device commanded to turn-on, irrespective of the process spread and of changes of temperature load conditions and of configuration of a plurality of output stages of a multichannel amplifier.

    68.
    发明专利
    未知

    公开(公告)号：IT1308597B1

    公开(公告)日：2002-01-08

    申请号：ITMI990257

    申请日：1999-02-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  CASSANI FABRIZIO

    IPC: H02J7/00 ,  H02M3/155

    Abstract: The step-up circuit has first and second input terminals for connection to a battery, first and second output terminals for connection to an electronic device to be fed by a DC/DC converter having a first and second input terminals connected respectively to the first and second input terminals of the step-up circuit. The second output terminal of the step-up circuit is connected to the second input terminal of the step-up circuit, one output terminal of the converter is connected to the first input terminal of the step-up circuit and the other output terminal of the converter is linked to the first output terminal of the step-up circuit, therefore, when operating, the output of the step-up circuit is the sum of the power of the battery and of the output of the converter. The step-up circuit is smaller, supplies the same output, is cheaper to produce and offers improved performance over the prior art.

    70.
    发明专利
    未知

    公开(公告)号：DE69413235D1

    公开(公告)日：1998-10-15

    申请号：DE69413235

    申请日：1994-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  MANDRINI TIOZIANA

    IPC: H03F3/68 ,  H03F3/30 ,  H03F3/45 ,  H03F3/50 ,  H03F3/72

    Abstract: A circuit assembly comprising an operational amplifier having an input stage (20) coupled directly to an output stage (21) in the form of a class AB amplifier is described. A compensating capacitance (Cc) is connected between a first input (IN1) and the output (OUT) of the output stage (21). A conventional feedback system (Rf1, Rf2) is provided between the output (OUT) of the output stage and an input of the input stage (20). Three switches (S1, S2, S3) enable the operational amplifier to be switched into three configurations: one in which it behaves in the manner of a conventional operational amplifier; one in which it behaves in the manner of a buffer; and one in which it has high impedance between its output terminals (OUT, earth). The class AB amplifier is constructed such that its final transistors (Qpf, Qnf) are controlled continuously and such that its polarisation circuits are substantially independent of those which provide current to the load (Zo), such that switching from one configuration to the other occurs without transients being generated.

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