公开(公告)号：ITTO20020288A1

公开(公告)日：2003-10-02

申请号：ITTO20020288

申请日：2002-04-02

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: H03K3/03 ,  H03L7/00

Abstract: An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.

公开(公告)号：DE69619501D1

公开(公告)日：2002-04-04

申请号：DE69619501

申请日：1996-03-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

IPC: G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G06F11/20

Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells, which has the particularity that it comprises: at least one bidirectional internal bus (1) for the transfer of data from and to the memory; a redundancy management line (2) that is associated with the internal bus (1); means (8) for enabling/disabling the transmission, over the internal bus (1), of the data from the memory toward the outside; means (11) for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and the redundancy line (2) during the reading of the memory matrix and during its programming.

公开(公告)号：ITTO20020288D0

公开(公告)日：2002-04-02

申请号：ITTO20020288

申请日：2002-04-02

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: H03K3/03 ,  H03L7/00

Abstract: An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.

公开(公告)号：DE69611550D1

公开(公告)日：2001-02-15

申请号：DE69611550

申请日：1996-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: G11C16/02 ,  G11C11/56

公开(公告)号：DE69128494T2

公开(公告)日：1998-04-16

申请号：DE69128494

申请日：1991-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

公开(公告)号：IT1240012B

公开(公告)日：1993-11-27

申请号：IT2015790

申请日：1990-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175 ,  H03K

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.