公开(公告)号：EP1052572A1

公开(公告)日：2000-11-15

申请号：EP99830286.3

申请日：1999-05-12

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Manstretta, Alessandro ,  Micheloni, Rino

IPC: G06F11/20

CPC classification number: G11C29/846

Abstract: Non-volatile memory device organised with memory cells that are arranged by row and by column, comprising at least a sector of matrix cells (100), row decoders (D) and column decoders suitable to decode address signals and to activate respectively said rows or said columns, at least a sector of redundancy cells (110) such that it is possible to substitute a row of said sector of matrix cells with a row of said sector of redundancy cells. Said non-volatile memory device comprises a local column decoder (L) for said matrix sector (100) and a local column decoder (L) for said redundancy sector (110). The local column decoders (L) are controlled by external signals so that said row of said redundancy sector (110) is activated simultaneously with said row of said matrix sector (100).

Abstract translation: 具有由行和列排列的存储单元组织的非易失性存储器件，包括至少一个矩阵单元（100）的扇区，行解码器（D）和适于解码地址信号的列解码器，并分别激活所述行或 所述列，至少一个冗余单元（110）的扇区，使得可以用所述冗余单元扇区的行来代替矩阵单元的所述扇区的一行。 所述非易失性存储器件包括用于所述矩阵扇区（100）的本地列解码器（L）和用于所述冗余扇区（110）的本地列解码器（L）。 本地列解码器（L）由外部信号控制，使得所述冗余扇区（110）的所述行与所述矩阵扇区（100）的所述行同时激活。

公开(公告)号：EP1028433A1

公开(公告)日：2000-08-16

申请号：EP99830071.9

申请日：1999-02-10

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C8/14 ,  G11C11/5621 ,  G11C16/08

Abstract: The multilevel memory (50) stores words formed by a plurality of binary subwords in a plurality of cells (63a-63p), each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors (56) divided into sector blocks (57), and are selected via a global row decoder (51), a global column decoder (54), and a plurality of local row decoders (58), which simultaneously supply a ramp voltage (V R ) to a biasing terminal of the selected cells. Threshold reading comparators (72a, 72b) are connected to the selected cells, and generate threshold attainment signals when the ramp voltage reaches the threshold value of the selected cells; switches (65a-65d), are arranged between the global word lines (52) and local word lines (59a-59d, 60a-60d), opening of the switches is individually controlled by the threshold attainment signals, thereby the local word lines are maintained at a the threshold voltage of the respective selected cell, after opening of the switches.

Abstract translation: 多级存储器（50）在多个单元（63a-63p）中存储由多个二进制子词形成的单词，每个单元具有相应的阈值。 小区被布置在小区行和列上，被分组成划分成扇区块（57）的扇区（56），并且经由全局行解码器（51），全局列解码器（54）和多个本地 行解码器（58​​），其同时向所选择的单元的偏置端子提供斜坡电压（VR）。 阈值读取比较器（72a，72b）连接到所选择的单元，并且当斜坡电压达到所选择的单元的阈值时产生阈值读取比较器（72a，72b） 开关（65a-65d）布置在全局字线（52）和本地字线（59a-59d，60a-60d）之间，开关的开启由阈值达到信号单独控制，从而本地字线 在打开开关之后保持在相应选定单元的阈值电压。

公开(公告)号：EP0973168A1

公开(公告)日：2000-01-19

申请号：EP99202169.1

申请日：1999-07-02

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F9/262 ,  G11C7/1006

Abstract: Non-volatile semiconductor memory device comprising an address buffer block (10), a matrix of memory cells (11) and an output buffer block (12), said address buffer block (10) receiving input signals (8) external to the memory device, that in a first operating mode are controlled by devices outside to the memory device, and transmitting signals to said matrix of memory cells (11), adapted to decode said received signals and to transmit in turn output decoded signals through said output buffer block (12). A command block (13;17,18,19) is provided with, activatable through an external control signal (16) that, once activated, puts the memory device in a second operating mode in which said command block (13;17,18,19) receives at least a part of said signals in output of said matrix of memory cells (11) and, after having processed them, transmits internal address signals (15) to said address buffer block (10), so to have a feedback inside said memory device capable of making the same able to execute a succession of instructions memorized in said matrix of memory cells (11) autonomously.

Abstract translation: 包括地址缓冲块（10），存储器单元（11）的矩阵和输出缓冲块（12）的非易失性半导体存储器件，所述地址缓冲器块（10）接收存储器件外部的输入信号（8） 在第一操作模式中由存储器件外部的器件控制，并将信号发送到存储器单元（11）的所述矩阵，适于对所述接收的信号进行解码，并通过所述输出缓冲器块（ 12）。 命令块（13; 17,18,19）具有可通过外部控制信号（16）激活的功能，一旦被激活，将存储器件置于第二操作模式，其中所述命令块（13; 17,18 ，19）在存储单元（11）的所述矩阵的输出中接收所述信号的至少一部分，并且在处理它们之后，将内部地址信号（15）发送到所述地址缓冲块（10），以便具有反馈 在所述存储器件内部能够使得能够自主地执行存储在存储器单元（11）的矩阵中的一系列指令。

公开(公告)号：EP0741387B1

公开(公告)日：2000-01-12

申请号：EP95830184.8

申请日：1995-05-05

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Campardo, Giovanni ,  Fusillo, Giuseppe ,  Silvagni, Andrea

IPC: G11C11/00 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C16/08

公开(公告)号：EP0932202A1

公开(公告)日：1999-07-28

申请号：EP97830741.1

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0251

Abstract: The invention relates to an ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate (2) and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply (Vcc) having a respective primary ground (GND), and from at least one secondary voltage supply (Vcc_IO) having a respective secondary ground (GND_IO). This network comprises essentially:

a first ESD protection element (15) for an input stage of the circuit structure;
a second ESD protection element (5) for an output stage of the circuit structure, the first (15) and second (5) protection elements having an input/output terminal (20) of the integrated circuit structure in common;
at least one ESD protection element (B0) between the primary supply (Vcc) and the primary ground (GND);
at least one ESD protection element (B) between the secondary supply (Vcc_IO) and the secondary ground (GND_IO).

Abstract translation: 本发明涉及一种用于集成在半导体衬底（2）中的CMOS电路结构的ESD保护网络，其包括形成在彼此电绝缘的各个衬底部分中的独立电路块，并且由至少一个初级电压源（Vcc ）具有相应的初级接地（GND），以及具有相应次级接地（GND_IO）的至少一个次级电压源（Vcc_IO）。 该网络基本上包括：用于电路结构的输入级的第一ESD保护元件（15） 用于所述电路结构的输出级的第二ESD保护元件（5），所述第一保护元件（15）和第二保护元件（5）具有所述集成电路结构的输入/输出端子（20）; 主电源（Vcc）和主接地（GND）之间的至少一个ESD保护元件（B0）; 在次级电源（Vcc_IO）和次级接地（GND_IO）之间的至少一个ESD保护元件（B）。

公开(公告)号：EP0915477A1

公开(公告)日：1999-05-12

申请号：EP97830576.1

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maccarrone, Marco ,  Zammattio, Matteo

IPC: G11C8/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells.
The method consists of duplicating the ATD signal into at least one pair of signals (ATD1,ATD2) and propagating such signals through separate parallel timing chains (6,9) at the ends of which the ATD signal is reinstated, the chains (6,9) being alternately active.

Abstract translation: 本发明涉及一种方法和用于产生用于半导体集成电子存储器装置的定时存储单元读取相的脉冲同步信号（ATD）的电路。 的脉冲信号（ATD）在检测到所述存储单元的地址输入端的多个的至少一个的逻辑状态的变化的产生。 该ATD信号复制到至少一个对信号（ATD1，ATD2），并通过ATD信号纯粹是表示在其端部的分开的平行的定时链（6,9）传播搜索信号的方法besteht，所述链（6， 9）交替地处于活动状态。

公开(公告)号：EP1845532B1

公开(公告)日：2009-04-01

申请号：EP06112526.6

申请日：2006-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C16/24 ,  G11C7/12 ,  G11C8/10

CPC classification number: G11C8/10 ,  G11C7/12 ,  G11C7/18 ,  G11C16/08 ,  G11C16/24 ,  G11C2207/002

公开(公告)号：EP1791245A1

公开(公告)日：2007-05-30

申请号：EP05111284.5

申请日：2005-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A charge pump circuit comprises at least one pump stage. Said pump stage includes a capacitor (C1,C2,C3;C'1,C'2,C'3) having a first plate and a second plate. The pump stage further includes a first circuital node (N1,N3,N5;N'2,N'4,N'6) connected to the first plate, a voltage of the first circuital node is forced to a first forced voltage (GND) during a forcing phase of the charge pump operation, and a second circuital node (N2,N4,N6;N'1,N'3,N'5) connected to the second plate, a voltage of the second circuital node is forced to a second forced voltage (Vdd) during the forcing phase. The voltages of the first and the second circuital nodes are free of changing with respect to the first and to the second forced voltage, respectively, except during said forcing phase. The pump stage still further includes a first forcing circuit (110,130,150;420,440,460) associated to the first circuital node, the first forcing circuit being activable for forcing the voltage of the first circuital node to the first forced voltage during the forcing phase, and a second forcing circuit (120,140,160;410,430,450) associated to the second circuital node, the second forcing circuit being activable for forcing the voltage of the second circuital node to the second forced voltage during the forcing phase.

Abstract translation: 电荷泵电路包括至少一个泵级。 所述泵级包括具有第一板和第二板的电容器（C1，C2，C3; C'1，C'2，C'3）。 泵级还包括连接到第一板的第一电路节点（N1，N3，N5; N'2，N'4，N'6），第一电路节点的电压被强制为第一强制电压（GND ）和连接到第二板的第二电路节点（N2，N4，N6; N'1，N'3，N'5），第二电路节点的电压被强制 在强制阶段到第二强制电压（Vdd）。 除了在所述强制阶段之外，第一和第二电路节点的电压分别相对于第一和第二强制电压没有变化。 所述泵级还包括与所述第一电路节点相关联的第一强制电路（110,130,150; 420,440,460），所述第一强制电路可激活以在所述强制阶段迫使所述第一电路节点的电压达到所述第一强制电压;以及第二强制电路 与所述第二电路节点相关联的所述第二强制电路（120,140,​​160; 410,430,450），所述第二强制电路是可激活的，以在所述强制阶段期间迫使所述第二电路节点的电压达到所述第二强制电压。

公开(公告)号：EP1713081A1

公开(公告)日：2006-10-18

申请号：EP06007497.8

申请日：2006-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni

IPC: G11C11/00 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/0433 ,  G11C16/26

Abstract: The invention relates to a nonvolatile electronic memory device (1) being monolithically integrated on a semiconductor substrate and of the Flash EEPROM type having a NAND architecture and comprising at least one memory matrix (11) organised in rows and columns of memory cells. Advantageously, the matrix comprises at least one portion (3) having smaller data storage capacity and faster access speed than the other portion (2).

Abstract translation: 本发明涉及一种非易失性存储器的电子设备（1）上的半导体基板和闪存EEPROM类型的具有NAND结构，并包括以行和存储单元的列组织的至少一个存储器矩阵（11）单片地集成。 有利地，所述矩阵包括至少一个部分（3），其具有更小的数据存储容量和更快的存取速度比其它部分（2）。

公开(公告)号：EP1327992B1

公开(公告)日：2005-03-30

申请号：EP02425009.4

申请日：2002-01-11

Applicant: STMicroelectronics S.r.l.

Inventor： Silvagni, Andrea ,  Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C16/08 ,  G11C8/16

CPC classification number: G11C16/08 ,  G11C2216/22