公开(公告)号：KR1020160041935A

公开(公告)日：2016-04-18

申请号：KR1020167003982

申请日：2014-07-14

Applicant: 광주과학기술원

Inventor： 윤명한 ,  이세영

IPC: B82B3/00 ,  B82Y15/00 ,  B82Y20/00

CPC classification number: H01L29/0676 ,  B81B2203/0361 ,  B81C1/00031 ,  B81C2201/0133 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32051 ,  H01L29/16

Abstract: 실리콘기판상에플라스틱입자들을균일한무작위패턴으로서로이격하여위치시키는단계; 상기플라스틱입자들사이에촉매층을형성하는단계; 상기플라스틱입자들을제거하는단계; 상기촉매층과접촉하는실리콘기판부위를수직적으로식각하는단계; 및상기촉매층을제거하는단계를포함하는, 실리콘나노와이어어레이의제조방법이제공된다. 본발명에따르면, 공정이단순하고비용효과적이며대면적공정으로대량생산이가능하고자원제한적인장소에서도나노와이어의제조가가능하며, 나노와이어의구조를독립적으로제어할수 있다.

Abstract translation: 提供了一种制造硅纳米线阵列的方法，包括以下步骤：将在硅衬底上以均匀的随机图案彼此分离的塑料颗粒定位; 在塑料颗粒之间形成催化剂层; 去除塑料颗粒; 垂直蚀刻接触催化剂层的硅衬底的部分; 并除去催化剂层。 本发明提供了一种简单且具有成本效益的方法，能够通过大的表面积处理进行批量生产，甚至能够在具有有限资源的位置制造纳米线，并且能够单独控制纳米线的结构。

公开(公告)号：KR1020080051716A

公开(公告)日：2008-06-11

申请号：KR1020060123293

申请日：2006-12-06

Applicant: 한국전자통신연구원

Inventor： 고상춘 ,  전치훈 ,  표현봉 ,  박선희

IPC: B81C1/00

CPC classification number: B81C1/00801 ,  B81C2201/0133 ,  B81C2201/0136

Abstract: A method for manufacturing a floating structure of a micro-electrochemical integrated system is provided to selectively etch a thick oxidation film by forming a micro-channel at high etching speed by isotropically etching a sacrificial layer. A method for manufacturing a floating structure of a micro-electrochemical integrated system includes the steps of: forming a sacrificial layer including a thin-film pattern(102A) with impurities doped on a substrate(100); forming a support film on the sacrificial layer; forming a structure to be floated on the support film through post processes; forming an etching hole(115) for exposing both sides of the thin-film pattern; and forming an air gap between the support film and the substrate by removing the sacrificial layer via the etching hole.

Abstract translation: 提供了一种用于制造微电化学集成系统的浮动结构的方法，以通过各向同性蚀刻牺牲层以高蚀刻速度形成微通道来选择性地蚀刻厚氧化膜。 一种用于制造微电化学集成系统的浮动结构的方法包括以下步骤：形成包括掺杂在衬底（100）上的杂质的薄膜图案（102A）的牺牲层; 在牺牲层上形成支撑膜; 通过后处理形成浮在支撑膜上的结构; 形成用于暴露薄膜图案的两侧的蚀刻孔（115）; 以及通过经由所述蚀刻孔去除所述牺牲层，在所述支撑膜和所述基板之间形成气隙。

公开(公告)号：EP2264468A3

公开(公告)日：2012-02-08

申请号：EP10012678.8

申请日：2000-07-13

Applicant: ION Geophysical Corporation

Inventor： Yu, Lianzhong ,  Goldberg, Howard D. ,  Ried, Robert P. ,  Yu, Duli

IPC: G01P9/04 ,  G01P15/135 ,  G02B26/00 ,  C23F1/00 ,  G03F7/26 ,  G03F7/00

CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

Abstract: The present invention provides merged-mask processes for fabricating micromachined devices in general and mirrored assemblies for use in optical scanning devices in particular. A method of fabricating a three dimensional structure, comprising, providing a substrate, applying a layer of a first masking material onto the substrate, applying a layer of a second masking material onto the layer of the first masking material, patterning the layer of the second masking material, applying a layer of a third masking material onto the portions not covered by the patterned layer of the second masking material, the layer of the third masking material is at least as thick as the combined thickness of the layers of the first and second masking materials, patterning the layers of the first and third masking materials, etching the exposed portions of the substrate, etching the exposed portions of the layers of the first and third masking materials and etching the exposed portions of the substrate.

Abstract translation: 本发明提供了用于一般地制造微机械装置和特别是用于光学扫描装置的镜面组件的合并掩模工艺。 一种制造三维结构的方法，包括：提供衬底，将第一掩蔽材料层施加到所述衬底上，将第二掩蔽材料层施加到所述第一掩模材料的所述层上，将所述第二掩模材料的所述层 掩模材料，将第三掩模材料层施加到未被第二掩模材料的图案化层覆盖的部分上，第三掩模材料的层至少与第一和第二掩模材料的层的组合厚度一样厚 掩模材料，图案化第一和第三掩模材料的层，蚀刻衬底的暴露部分，蚀刻第一和第三掩模材料的层的暴露部分并蚀刻衬底的暴露部分。

公开(公告)号：EP1764830B1

公开(公告)日：2012-01-25

申请号：EP05447238.6

申请日：2005-10-21

Applicant: IMEC

Inventor： Beyer, Gerald

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

公开(公告)号：EP2046677B1

公开(公告)日：2011-10-19

申请号：EP07789096.0

申请日：2007-08-02

Applicant: Memsstar Limited

Inventor： O'HARA, Anthony

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81C2201/0133

Abstract: A controlled method of releasing a microstructure comprising a silicon oxide layer located between a substrate layer and a layer to be released from the silicon oxide layer is described. The method comprises the step of exposing the silicon oxide layer to a hydrogen fluoride vapour in a process chamber having controlled temperature and pressure conditions. A by- product of this reaction is water which also acts as a catalyst for the etching process. It is controlled employment of this inherent water source that results in a condensed fluid layer forming, and hence etching taking place, only on the exposed surfaces of the oxide layer. The described method therefore reduces the risk of the effects of capillary induced stiction within the etched microstructure and/or corrosion within the microstructure and the process chamber itself.

公开(公告)号：EP2264468A2

公开(公告)日：2010-12-22

申请号：EP10012678.8

申请日：2000-07-13

Applicant: ION Geophysical Corporation

Inventor： Yu, Lianzhong ,  Goldberg, Howard D. ,  Ried, Robert P. ,  Yu, Duli

IPC: G01P9/04 ,  G01P15/135 ,  G02B26/00 ,  C23F1/00 ,  G03F7/26 ,  G03F7/00

CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

Abstract: The present invention provides merged-mask processes for fabricating micromachined devices in general and mirrored assemblies for use in optical scanning devices in particular. A method of fabricating a three dimensional structure, comprising, providing a substrate, applying a layer of a first masking material onto the substrate, applying a layer of a second masking material onto the layer of the first masking material, patterning the layer of the second masking material, applying a layer of a third masking material onto the portions not covered by the patterned layer of the second masking material, the layer of the third masking material is at least as thick as the combined thickness of the layers of the first and second masking materials, patterning the layers of the first and third masking materials, etching the exposed portions of the substrate, etching the exposed portions of the layers of the first and third masking materials and etching the exposed portions of the substrate.

公开(公告)号：EP1395835B1

公开(公告)日：2006-08-16

申请号：EP02731255.2

申请日：2002-04-05

Applicant: Honeywell International Inc.

Inventor： MALAMETZ, David

IPC: G01P15/08 ,  G01P1/00 ,  B81B3/00

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2203/0181 ,  B81B2203/058 ,  B81C2201/0133 ,  G01P1/006 ,  G01P15/097

Abstract: An apparatus and method for suspending and strain isolating a structure is provided, the apparatus having a first elongated flexure having first and second ends structured for connection to a support structure, and a second elongated flexure having first and second ends structured for connection to a structure to be isolated from the support structure. A portion of the second flexure intermediate the first and second ends thereof is interconnected to a portion of the first flexure intermediate the first and second ends thereof. The strain relief structure may be used in an accelerometer. The structure may have a H or X form, where the legs represent the elongated flexures.

公开(公告)号：EP1234799B1

公开(公告)日：2006-06-07

申请号：EP02003900.4

申请日：2002-02-21

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yasuda, Susumu ,  Mizutani, Hidemasa ,  Yagi, Takayuki ,  Shimada, Yasuhiro ,  Hirose, Futoshi ,  Kato, Takahisa

IPC: B81B3/00 ,  B81C1/00 ,  G02B26/10

CPC classification number: G02B26/105 ,  B81B3/0051 ,  B81B3/0067 ,  B81B2201/038 ,  B81B2201/042 ,  B81B2203/0181 ,  B81B2203/058 ,  B81C2201/0133 ,  G02B26/0841 ,  Y10S359/90 ,  Y10S359/904

公开(公告)号：EP1196788A4

公开(公告)日：2003-01-15

申请号：EP00945370

申请日：2000-07-13

Applicant: INPUT OUTPUT INC

Inventor： YU LIANZHONG ,  RIED ROBERT P ,  GOLDBERG HOWARD D ,  YU DULI

IPC: G02B26/10 ,  B81B3/00 ,  B81C1/00 ,  C23F1/02 ,  G01P9/04 ,  G02B26/08 ,  G03F7/20 ,  C23F1/00 ,  G01P15/135 ,  G02B26/00 ,  G03F7/00 ,  G03F7/26

CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

Abstract: The present invention provides merged-mask processes for fabricating micro-machined devices in general and mirrored assemblies for use in optical scanning devices in particular. The process includes (a) providing a substrate having a predetermined thickness; (b) applying a first masking layer on a first portion of the substrate and a second masking layer on a second portion of the substrate, said second masking layer being at least as thick as the first masking layer; (c) etching a portion of the second masking layer to provide a first exposed portion of the substrate; (d) etching the first exposed portion of the substrate to a first depth; (e) etching the second masking layer to provide a second exposed portion of the substrate; and (f) etching simultaneously the first exposed portion of the substrate to a second depth and the second exposed portion of the substrate to a first depth. The process further comprises patterning the first masking layer before applying the second masking layer to provide the second portion of the substrate for etching and etching the first masking layer to expose the second portion of the substrate. The first and second masking layers are applied prior to etching the substrate.

Abstract translation: 本发明提供了用于一般地制造微机械装置和特别是用于光学扫描装置的镜面组件的合并掩模工艺。 一种制造三维结构的方法，包括：提供衬底，将第一掩蔽材料层施加到所述衬底上，将第二掩蔽材料层施加到所述第一掩模材料的所述层上，将所述第二掩模材料的所述层 掩模材料，将第三掩模材料层施加到未被第二掩模材料的图案化层覆盖的部分上，第三掩模材料的层至少与第一和第二掩模材料的层的组合厚度一样厚 掩模材料，图案化第一和第三掩模材料的层，蚀刻衬底的暴露部分，蚀刻第一和第三掩模材料的层的暴露部分并蚀刻衬底的暴露部分。

公开(公告)号：EP1196788A1

公开(公告)日：2002-04-17

申请号：EP00945370.5

申请日：2000-07-13

Applicant: Input Output, Inc.

Inventor： YU, Lianzhong,13906 NE 9th PL ,  RIED, Robert, P. ,  GOLDBERG, Howard, D. ,  YU, Duli

IPC: G01P9/04 ,  G01P15/135 ,  G02B26/00 ,  C23F1/00 ,  G03F7/26

CPC classification number: G02B26/0816 ,  B81B2201/042 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  C23F1/02

Abstract: The present invention provides merged-mask processes for fabricating micro-machined devices in general and mirrored assemblies for use in optical scanning devices in particular. The process includes (a) providing a substrate having a predetermined thickness; (b) applying a first masking layer on a first portion of the substrate and a second masking layer on a second portion of the substrate, said second masking layer being at least as thick as the first masking layer; (c) etching a portion of the second masking layer to provide a first exposed portion of the substrate; (d) etching the first exposed portion of the substrate to a first depth; (e) etching the second masking layer to provide a second exposed portion of the substrate; and (f) etching simultaneously the first exposed portion of the substrate to a second depth and the second exposed portion of the substrate to a first depth. The process further comprises patterning the first masking layer before applying the second masking layer to provide the second portion of the substrate for etching and etching the first masking layer to expose the second portion of the substrate. The first and second masking layers are applied prior to etching the substrate.