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公开(公告)号：US5756901A
公开(公告)日：1998-05-26
申请号：US718603
申请日：1996-09-24
Applicant: Juergen Kurle , Karsten Funk , Franz Laermer , Michael Offenberg , Andrea Schilp
Inventor： Juergen Kurle , Karsten Funk , Franz Laermer , Michael Offenberg , Andrea Schilp
CPC classification number: B81B7/007 , B81C1/0019 , G01P15/0802 , G01P15/125 , B81B2201/0235 , B81B2203/033 , B81C2201/0136 , B81C2203/0118 , G01P2015/0814
Abstract: In a sensor and a method for manufacturing a sensor, a movable element is patterned out of a silicon layer and is secured to a substrate. The conducting layer is subdivided into various regions, which are electrically insulated from one another. The electrical connection between the various regions of the silicon layer is established by a conducting layer, which is arranged between a first and a second insulating layer.
Abstract translation: 在传感器和制造传感器的方法中，可移动元件被图案化为硅层并固定到基底。 导电层被细分成彼此电绝缘的各个区域。 通过布置在第一和第二绝缘层之间的导电层来建立硅层的各个区域之间的电连接。
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公开(公告)号：KR1020000062378A
公开(公告)日：2000-10-25
申请号：KR1019997005924
申请日：1998-01-05
Applicant: 지멘스 악티엔게젤샤프트
IPC: G01P15/08
CPC classification number: B81C1/00595 , B81B2203/0127 , B81B2203/0315 , B81C2201/0136 , G01P15/0802
Abstract: 본발명은공동부(9)내에형성된박막(7)을갖는마이크로메카닉반도체장치및 그것의제조방법에관한것이다. 상기박막(7)은반도체장치의기판(1)내에또는기판(1)상에배치된연속에피텍셜층내에결정층으로형성된다. 박막(7)은지지부(6)의가장자리영역에놓이고, 대향지지부(5)상에지지된커버층(4)으로덮힌다. 한편으로지지부(6) 및대향지지부(5)가, 다른한편으로박막(7)이미리결정된습식-케미칼에칭제와상이한에칭율을갖는재료로제조되고, 바람직하게상이한도핑재료로이루어진다.
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公开(公告)号：KR1019970007108B1
公开(公告)日：1997-05-02
申请号：KR1019930023136
申请日：1993-11-02
Applicant: 대한민국경북대학교센서기술연구소 , 만도기계 주식회사
Inventor： 이종현
IPC: H01L21/302
CPC classification number: B81B3/0051 , B81C1/00595 , B81C2201/0136 , Y10S438/96
Abstract: A method of fabricating a fine structured silicon stopper using double diffusion includes an oxidation step of growing an oxide layer 2 on an n-type substrate 1, a first diffusion step of forming a window in the oxide layer and forming two separate first n+ diffusion regions 3 through the first selective diffusion according to impurity implantation, a second diffusion step of removing the oxide layer, defining the region between the two first diffusion regions with an oxide layer 2" and performing the second selective diffusion to form a second n+ diffusion region 4 for a stopper, having a depth of 0.5-5 m, an epitaxial layer growing step of removing the oxide layer 2" and growing an n-type epitaxial layer 5 on the overall surface of the substrate, an anode reaction step of selectively etching the n-type epitaxial layer, leaving only a bridge-type fine structure, to expose the n+ diffusion region and carrying out anode reaction to make the first and second n+ diffusion regions 3 and 4 into a porous silicon layer 6, and an etching step of etching the porous silicon layer using an etchant to form the fine structure.
Abstract translation: 使用双扩散制造精细结构硅塞的方法包括在n型基板1上生长氧化物层2的氧化步骤，在氧化物层中形成窗口并形成两个单独的第一n +扩散区域的第一扩散步骤 3，通过根据杂质注入的第一选择性扩散，第二扩散步骤，去除氧化物层，在氧化物层2“之间限定两个第一扩散区域之间的区域，并执行第二选择扩散以形成第二n +扩散区域4 对于深度为0.5-5μm的塞子，除去氧化物层2的外延层生长步骤和在基板的整个表面上生长n型外延层5的阳极反应步骤，选择性地蚀刻 n型外延层，仅留下桥型精细结构，露出n +扩散区域并进行阳极反应，以使第一和第二n +扩散区域3和4 进入多孔硅层6，以及使用蚀刻剂蚀刻多孔硅层以形成精细结构的蚀刻步骤。
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公开(公告)号：KR1020080051716A
公开(公告)日：2008-06-11
申请号：KR1020060123293
申请日：2006-12-06
Applicant: 한국전자통신연구원
IPC: B81C1/00
CPC classification number: B81C1/00801 , B81C2201/0133 , B81C2201/0136
Abstract: A method for manufacturing a floating structure of a micro-electrochemical integrated system is provided to selectively etch a thick oxidation film by forming a micro-channel at high etching speed by isotropically etching a sacrificial layer. A method for manufacturing a floating structure of a micro-electrochemical integrated system includes the steps of: forming a sacrificial layer including a thin-film pattern(102A) with impurities doped on a substrate(100); forming a support film on the sacrificial layer; forming a structure to be floated on the support film through post processes; forming an etching hole(115) for exposing both sides of the thin-film pattern; and forming an air gap between the support film and the substrate by removing the sacrificial layer via the etching hole.
Abstract translation: 提供了一种用于制造微电化学集成系统的浮动结构的方法，以通过各向同性蚀刻牺牲层以高蚀刻速度形成微通道来选择性地蚀刻厚氧化膜。 一种用于制造微电化学集成系统的浮动结构的方法包括以下步骤：形成包括掺杂在衬底（100）上的杂质的薄膜图案（102A）的牺牲层; 在牺牲层上形成支撑膜; 通过后处理形成浮在支撑膜上的结构; 形成用于暴露薄膜图案的两侧的蚀刻孔（115）; 以及通过经由所述蚀刻孔去除所述牺牲层，在所述支撑膜和所述基板之间形成气隙。
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公开(公告)号：KR100210848B1
公开(公告)日：1999-07-15
申请号：KR1019960035539
申请日：1996-08-26
Applicant: 현대반도체 주식회사
Inventor： 이석수
IPC: H01L21/306
CPC classification number: B81C1/0015 , B81B2203/0136 , B81C2201/0114 , B81C2201/0136
Abstract: 본 발명은 실리콘 미세 기계의 제조방법에 관한 것으로서 제1도전형의 실리콘기판 상의 소정 부분에 불순물이 고농도로 도핑된 확산영역을 형성하는 공정과, 상기 확산영역을 포함하는 실리콘기판 상에 에피택셜층을 형성하고 상기 에피택셜층 상에 산화막을 형성하는 공정과, 상기 실리콘기판의 하부 표면에 오믹접촉층을 형성하는 공정과, 상기 산화막을 상기 확산영역의 소정 부분과 대응하는 부분이 다수 개의 줄무늬 형태를 이루도록 패터닝하여 상기 에피택셜층의 소정 부분을 노출시키는 공정과, 상기 산화막을 마스크로 사용하여 상기 에피택셜층의 노출된 부분을 식각하여 다수 개의 줄무늬 형태의 빔을 형성하고 상기 산화막을 제거하는 공정과, 상기 다수 개의 빔 하부의 확산영역을 제거하는 공정을 구비한다. 따라서, 실리콘 기판의 하부 표면을 연마하지 않으므로 실리콘기판이 오염되는 것을 방지할 수 있으며 빔이 휘어질 공간을 한정하기 위해 확산영역을 전기화학적 식각방법으로 짧은 시간에 제거할 수 있으며, 또한, 에피택셜층의 상부만을 마스크 정렬하여 빔을 형성하고 확산영역을 마스크 없이 제거하므로 정렬 오차의 발생을 방지할 수 있다.
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Patent Agency Ranking
公开(公告)号：JP6414605B2
公开(公告)日：2018-10-31
申请号：JP2016575358
申请日：2015-05-18
Applicant: TDK株式会社
Inventor： ロムバッハ, ピルミン ヘルマン オットー
CPC classification number: H04R19/04 , B81B3/0075 , B81B2201/0257 , B81C1/00531 , B81C2201/0136 , H04R19/005 , H04R31/00 , H04R31/006 , H04R2201/003
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公开(公告)号：JP2017520193A
公开(公告)日：2017-07-20
申请号：JP2016575358
申请日：2015-05-18
Applicant: エプコス アクチエンゲゼルシャフトEpcos Ag , エプコス アクチエンゲゼルシャフトEpcos Ag
Inventor： ピルミン ヘルマン オットー ロムバッハ， , ピルミン ヘルマン オットー ロムバッハ，
CPC classification number: H04R19/04 , B81B3/0075 , B81B2201/0257 , B81C1/00531 , B81C2201/0136 , H04R19/005 , H04R31/00 , H04R31/006 , H04R2201/003
Abstract: 改善されたマイクロフォンおよびこれを製造する方法が提示され、これらは局所的に異なるエッチング速度を有する犠牲層を用いている。【選択図】図22
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公开(公告)号：JP5222399B2
公开(公告)日：2013-06-26
申请号：JP2011512908
申请日：2009-04-21
Inventor： クラーマー トアステン , アーレス マルクス , グルントマン アーミン , クネーゼ カトリン , ベンツェル フーベルト , シュアマン グレゴア , アームブルスター ズィモン
CPC classification number: B81C1/00158 , B81B2201/0257 , B81B2201/0264 , B81C2201/0115 , B81C2201/0136 , G01L9/0042
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公开(公告)号：JP2004106116A
公开(公告)日：2004-04-08
申请号：JP2002271644
申请日：2002-09-18
Applicant: Fujitsu Ltd , 富士通株式会社
Inventor： OKUDA SHOJI , TOKUNAGA HIROSHI , TSUBOI OSAMU
CPC classification number: B81C1/0019 , B81B2201/0271 , B81C2201/0136 , B81C2201/019
Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a micromachine manufacturing the micromachine with a torsion bar at high yield.
SOLUTION: This manufacturing method for the micromachine is provided with processes of: embedding an oxide film 54 in a first semiconductor substrate 6; sticking the first semiconductor substrate to a second semiconductor substrate 8 via an insulating film 18; forming a first mask 66 opening the first region and second regions in the both sides of the first region; etching the first semiconductor substrate using the first mask 66 and the oxide film 54 as the masks, forming a spring portion 20a integrally formed with the first semiconductor substrate between the oxide film and the insulating film, and forming the torsion bar 16; forming a second mask 74 opening the first region and the second regions; etching the second semiconductor substrate using the second mask 74, and etching the insulating film 18 in the first region and the second region.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP4753326B2
公开(公告)日：2011-08-24
申请号：JP2000208650
申请日：2000-07-10
Inventor： フィンクバイナー シュテファン , ベンツェル フーベルト
CPC classification number: B81C1/00158 , B81C2201/0136
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