公开(公告)号：US11952268B2

公开(公告)日：2024-04-09

申请号：US17304094

申请日：2021-06-14

Applicant: Lawrence Semiconductor Research Laboratory, Inc.

Inventor： Chantal Arena ,  Nupur Bhargava ,  Alec Fischer

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00476 ,  B81B3/0072 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0177

Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

公开(公告)号：US20180143352A1

公开(公告)日：2018-05-24

申请号：US15325448

申请日：2016-12-28

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Guowei ZHA

IPC: G02B1/113 ,  C03C17/34 ,  C03C17/23 ,  C01B32/186 ,  C01B32/188 ,  B32B3/30 ,  B81C1/00 ,  B82B3/00

CPC classification number: G02B1/113 ,  B32B3/30 ,  B81C1/00555 ,  B81C2201/0177 ,  B82B3/0095 ,  C01B32/186 ,  C01B32/188 ,  C01B2204/20 ,  C03C17/23 ,  C03C17/3441 ,  C03C2217/734 ,  G02B1/118

Abstract: A manufacturing method of micro-nano structure antireflective coating layer and a display apparatus thereof are described. The method includes providing a substrate, forming a silicon oxide layer on the substrate, forming a graphene layer with a hexagonal honeycomb lattice on the silicon oxide layer, and forming a bottom surface of the antireflective coating layer in the nucleation points by serving the graphene layer as a growing base layer, wherein a diffusion length and an atomic mass of diffusion atoms of the antireflective coating layer are decreased with time by a gradient growing manner to form a upper surface of the antireflective coating layer.

公开(公告)号：US20160137485A1

公开(公告)日：2016-05-19

申请号：US14201453

申请日：2014-03-07

Applicant: Robert Bosch GmbH

Inventor： Andrew Graham ,  Gary Yama ,  Gary O'Brien

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.

Abstract translation: 在一个实施例中，形成平面外电极的方法包括在器件层的上表面上形成氧化物层，蚀刻限定延伸穿过氧化物层的沟槽的蚀刻停止周界，在第一帽层部分上形成 氧化物层的上表面，并且在蚀刻停止周界内限定沟槽，蚀刻延伸穿过第一盖层部分并停止在氧化物层处的第一电极周界，限定沟槽，在第一电极周界限定沟槽内沉积第一材料部分，沉积 在沉积的第一材料部分上方的第二盖层部分，以及用蚀刻停止部分提供横向蚀刻停止物的一部分氧化物层的蒸气。

公开(公告)号：US08558643B2

公开(公告)日：2013-10-15

申请号：US13468052

申请日：2012-05-10

Applicant: Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

Inventor： Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

IPC: H03H9/24 ,  H03H3/013 ,  H01L29/06 ,  H01L21/00

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0177 ,  G06F17/5045 ,  H03H9/02448 ,  H03H9/2447 ,  H03H2009/2442

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract translation: 本发明涉及一种微机械装置，其包括能够偏转或谐振并且包括具有不同材料特性的至少两个区域的半导体元件和功能性耦合到所述半导体元件的驱动或感测装置。 根据本发明，所述区域中的至少一个包括一种或多种n型掺杂剂，并且所述区域的相对体积，掺杂浓度，掺杂剂和/或晶体取向被构造成使得广义刚度的温度敏感度 在区域的至少一个温度下符号相反，半导体元件的整体刚度的总体温度漂移在100℃的温度范围内为50ppm以下。该器件可以是谐振器。 还公开了一种设计该设备的方法。

公开(公告)号：US20110209970A1

公开(公告)日：2011-09-01

申请号：US13029898

申请日：2011-02-17

Applicant: Takahiro Masuda ,  Naoki Yoshitake ,  Kenichi Hinuma ,  Junya Yamamoto ,  Takashi Fujisawa ,  Takeshi Fujiwara

Inventor： Takahiro Masuda ,  Naoki Yoshitake ,  Kenichi Hinuma ,  Junya Yamamoto ,  Takashi Fujisawa ,  Takeshi Fujiwara

IPC: H01H59/00 ,  H01H11/00

CPC classification number: H01H1/06 ,  B81B2201/014 ,  B81C1/00166 ,  B81C2201/0177 ,  B81C2201/0181 ,  B81C2201/0184 ,  H01H1/0036 ,  H01H2001/0052 ,  Y10T29/49105

Abstract: A switch and a relay include a contact with a smooth contacting surface. A side surface of a fixed contact faces a side surface of a movable contact. The fixed contact has an insulating layer and a base layer stacked on a fixed contact substrate, and a first conductive layer formed thereon through electrolytic plating. The side surface of the first conductive layer that faces the movable contact becomes the fixed contact (contacting surface). The movable contact has an insulating layer and a base layer stacked on the movable contact substrate, and a movable contact formed thereon through electrolytic plating. A side surface of a second conductive layer that faces the fixed contact becomes the movable contact (contacting surface). The fixed contact and the movable contact have surfaces that contact the side surfaces of the mold portion when growing the first and second conductive layers through electrolytic plating.

Abstract translation: 开关和继电器包括具有光滑接触表面的触点。 固定触点的侧表面面对活动触点的侧表面。 固定触点具有层叠在固定接触基板上的绝缘层和基层，以及通过电解电镀形成在其上的第一导电层。 第一导电层的面对可动触点的侧表面成为固定触点（接触面）。 可动触头具有堆叠在可动触点基板上的绝缘层和基极层，以及通过电解电镀形成的可动触点。 面对固定触点的第二导电层的侧表面成为可动触头（接触面）。 固定触点和可动触点具有通过电解电镀生长第一和第二导电层时与模具部分的侧表面接触的表面。

公开(公告)号：US07998776B1

公开(公告)日：2011-08-16

申请号：US12910801

申请日：2010-10-23

Applicant: Gang Li ,  Wei Hu

Inventor： Gang Li ,  Wei Hu

IPC: H01L21/00

CPC classification number: G01L9/0042 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0376 ,  B81C1/00182 ,  B81C2201/0132 ,  B81C2201/0177 ,  G01L9/0045 ,  G01P15/123 ,  G01P2015/0828

Abstract: A method for manufacturing a MEMS sensor and a thin film thereof includes steps of etching a top surface of a single-crystal silicon wafer in combination of a deposition process, an isotropic DRIE process, a wet etching process and a back etching process in order to form a pressure-sensitive single-crystal silicon film, a cantilever beam, a mass block, a front chamber, a back chamber and trenches connecting the front and the back chambers. The single-crystal silicon film is prevented from etching so that the thickness thereof can be well controlled. The method of the present invention can be used to replace the traditional method which forms the back chamber and the pressure-sensitive single-crystal silicon film from the bottom surface of the silicon wafer.

Abstract translation: MEMS传感器及其薄膜的制造方法包括以下步骤：结合沉积工艺，各向同性DRIE工艺，湿蚀刻工艺和背蚀刻工艺来蚀刻单晶硅晶片的顶表面，以便 形成压敏单晶硅膜，悬臂梁，质量块，前室，后室和连接前室和后室的沟槽。 防止单晶硅膜蚀刻，从而可以良好地控制其厚度。 本发明的方法可以用于代替从硅晶片的底表面形成后室和压敏单晶硅膜的传统方法。

公开(公告)号：US06928879B2

公开(公告)日：2005-08-16

申请号：US10375645

申请日：2003-02-26

Applicant: Aaron Partridge ,  Markus Lutz

Inventor： Aaron Partridge ,  Markus Lutz

IPC: B81B3/00 ,  G01L9/00 ,  H01L29/84

CPC classification number: B81C1/00047 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0145 ,  G01L9/0045 ,  G01L9/0054 ,  G01L9/0073

Abstract: A method for making a pressure sensor by providing a wafer including a base silicon layer, a buried sacrificial layer, and a top silicon layer. The top silicon layer is arranged over the buried sacrificial layer and the buried sacrificial layer is arranged over the base silicon layer. Etching vents through the top silicon layer to the buried sacrificial layer and removing a portion of the buried sacrificial layer. Depositing silicon to seal the vents and arranging a strain gauge or a capacitance contact on the wafer. A method for making a pressure sensor including providing a bulk wafer and depositing a sacrificial layer on the bulk wafer. Depositing silicon on the sacrificial layer and the bulk wafer to form an encapsulation layer. Etching vents through the encapsulation layer to the sacrificial layer and removing the sacrificial layer. Closing the vents with a silicon deposition and arranging a strain gauge or a capacitance contact on the encapsulation layer. A pressure sensing device including a substrate, an encapsulation layer with vents, and voids between the substrate and the encapsulation layer. A portion of the encapsulation layer above the voids forms a membrane and deposited silicon plugs fill the vents. A strain gauge or a top capacitive contact arranged on the membrane.

公开(公告)号：US20050142688A1

公开(公告)日：2005-06-30

申请号：US11064658

申请日：2005-02-23

Applicant: Aaron Partridge ,  Markus Lutz

Inventor： Aaron Partridge ,  Markus Lutz

IPC: B81B3/00 ,  G01L9/00 ,  H01L29/84 ,  H01L21/00

CPC classification number: B81C1/00047 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0145 ,  G01L9/0045 ,  G01L9/0054 ,  G01L9/0073

Abstract: A method for making a pressure sensor by providing a wafer including a base silicon layer, a buried sacrificial layer, and a top silicon layer. The top silicon layer is arranged over the buried sacrificial layer and the buried sacrificial layer is arranged over the base silicon layer. Etching vents through the top silicon layer to the buried sacrificial layer and removing a portion of the buried sacrificial layer. Depositing silicon to seal the vents and arranging a strain gauge or a capacitance contact on the wafer. A method for making a pressure sensor including providing a bulk wafer and depositing a sacrificial layer on the bulk wafer. Depositing silicon on the sacrificial layer and the bulk wafer to form an encapsulation layer. Etching vents through the encapsulation layer to the sacrificial layer and removing the sacrificial layer. Closing the vents with a silicon deposition and arranging a strain gauge or a capacitance contact on the encapsulation layer. A pressure sensing device including a substrate, an encapsulation layer with vents, and voids between the substrate and the encapsulation layer. A portion of the encapsulation layer above the voids forms a membrane and deposited silicon plugs fill the vents. A strain gauge or a top capacitive contact arranged on the membrane.

Abstract translation: 一种通过提供包括基底硅层，掩埋牺牲层和顶部硅层的晶片来制造压力传感器的方法。 顶层硅层布置在掩埋牺牲层上方，掩埋牺牲层布置在基底硅层上。 蚀刻通孔通过顶部硅层到掩埋牺牲层并去除一部分掩埋牺牲层。 沉积硅以密封通风口并在晶片上布置应变计或电容接触。 一种用于制造压力传感器的方法，包括提供体晶片并在体晶片上沉积牺牲层。 在牺牲层和体晶片上沉积硅以形成封装层。 蚀刻通过封装层到达牺牲层并去除牺牲层。 用硅沉积封闭通风口，并在封装层上布置应变计或电容接触。 一种压力感测装置，包括基底，通气孔的封装层以及基底和封装层之间的空隙。 空隙之上的封装层的一部分形成膜并且沉积的硅塞填充通风口。 布置在膜上的应变计或顶部电容接触。

公开(公告)号：US20040121564A1

公开(公告)日：2004-06-24

申请号：US10328922

申请日：2002-12-23

Applicant: Motorola Inc.

Inventor： Bishnu Gogoi

IPC: H01L021/00 ,  H01L021/20 ,  H01L021/36

CPC classification number: B81B3/001 ,  B81C2201/0109 ,  B81C2201/0177

Abstract: A method for creating a semiconductor structure is provided. In accordance with the method, a semiconductor substrate (101) is provided over which is disposed a sacrificial layer (103), and which has a thin single crystal semiconductor layer (105) disposed over the sacrificial layer (103). An opening (107) is then created which extends through the semiconductor layer (105) and into the sacrificial layer (103). The semiconductor layer (105) is then epitaxially grown to a suitable device thickness, thereby resulting in a device layer. The semiconductor layer is grown such that the resulting device layer extends over the opening (107), and such that the surface of the portion of the device layer extending over the opening is single crystal silicon.

Abstract translation: 提供了一种用于制造半导体结构的方法。 根据该方法，提供半导体衬底（101），在其上设置有牺牲层（103），并且具有设置在牺牲层（103）上方的薄单晶半导体层（105）。 然后产生延伸穿过半导体层（105）并进入牺牲层（103）的开口（107）。 然后将半导体层（105）外延生长至合适的器件厚度，由此产生器件层。 生长半导体层使得所得到的器件层在开口（107）上延伸，并且使得在开口上延伸的器件层的部分的表面是单晶硅。

公开(公告)号：US6109106A

公开(公告)日：2000-08-29

申请号：US126625

申请日：1998-07-30

Applicant: Paolo Ferrari ,  Benedetto Vigna ,  Pietro Montanini ,  Marco Ferrera

Inventor： Paolo Ferrari ,  Benedetto Vigna ,  Pietro Montanini ,  Marco Ferrera

IPC: G01P9/04 ,  B81B3/00 ,  G01C19/56 ,  G01P15/08 ,  G01P15/125 ,  H01L21/762 ,  H01L21/764 ,  H01L41/08

CPC classification number: H01L21/764 ,  B81C1/00246 ,  G01P15/0802 ,  G01P15/125 ,  H01L21/76202 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0735 ,  B81C2203/0778 ,  G01P2015/0814

Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Abstract translation: 从外延层开始形成形成地震质量块的移动体，并且由具有高密度的钨的加权区域覆盖。 为了制造质量，在衬底中形成掩埋的导电区域。 然后，同时，在要形成可移动物体的区域中形成牺牲区域，并且在掩埋的导电区域上形成氧化物绝缘区域，以便部分地覆盖它们。 然后使用核区域生长外延层。 沉积和限定钨层，并且使用碳化硅层作为掩模，限定悬浮结构。 最后，去除牺牲区域，形成气隙。