公开(公告)号：JP2016025298A

公开(公告)日：2016-02-08

申请号：JP2014150485

申请日：2014-07-24

Applicant: セイコーエプソン株式会社

Inventor： 近藤 学

IPC: H01L23/04 ,  H03B5/32 ,  H03H9/02 ,  H03H3/02 ,  H05K1/18 ,  H01L23/50

CPC classification number: H05K1/11 ,  H01L23/49811 ,  H03B5/32 ,  H03H9/0528 ,  H03H9/09 ,  H05K1/111 ,  H05K1/181 ,  H05K3/4015 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/32 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/15312 ,  H01L2924/161 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/1904 ,  H03H9/0547 ,  H03H9/1021 ,  H05K2201/09209 ,  H05K2201/10083

Abstract: 【課題】電子部品本体から突出するリード端子の付け根部分に集中する応力を緩和し、リード端子の付け根部分の変形や、破損を防止する電子部品を提供する。 【解決手段】電子部品としての水晶発振器1は、第1の基板11に設けられている接続端子25と接続されている接続パッド21および接続パッド21から延在されたリード部22を含むリード端子24を有する。リード端子24は、接続端子25と接続される第1面61とその裏面の第2面62と側面である第3面63とを備える。リード部22には、第1面61または第2面62と交わる方向に屈曲する第1屈曲部51と、第3面63と交わる方向に屈曲する第2屈曲部52と、第2屈曲部52とリード部22の端との間に、第1面61または第2面62と交わる方向に屈曲する第3屈曲部53を備えている。 【選択図】図1

Abstract translation: 要解决的问题：提供一种电子部件，其中防止引线端子的根部变形或损坏，通过放松集中在从电子部件体突出的引线端子的根部上的应力。解决方案：晶体振荡器 如图1所示，作为电子部件具有引线端子24，引线端子24包括连接焊盘21，连接焊盘21与设置在第一基板11上的连接端子25连接，引线22从连接焊盘21延伸。引线端子24包括第一面61 与连接端子25连接，其背面具有第二面62和第三面63即侧面。 引线22包括沿与第一面61或第二面62交叉的方向弯曲的第一弯曲部51，与第三面63交叉的方向弯曲的第二弯曲部52和与第一面部61交叉的方向弯曲的第三弯曲部53 或第二面62，在第二弯曲部52和引线22之间。选择的图示：图1

公开(公告)号：US11737209B2

公开(公告)日：2023-08-22

申请号：US17574551

申请日：2022-01-13

Applicant: Unimicron Technology Corp.

Inventor： Chih-Chiang Lu ,  Chi-Min Chang ,  Shao-Chien Lee ,  Jun-Rui Huang ,  Ming-Ting Chang

IPC: H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/024 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/10 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/0183 ,  H05K2201/09209 ,  H05K2203/0502

Abstract: A circuit board includes a first dielectric material, a second dielectric material, a third dielectric material, a first external circuit layer, a second external circuit layer, multiple conductive structures, and a conductive via structure. Dielectric constants of the first, the second and the third dielectric materials are different. The first and the second external circuit layers are respectively disposed on the first and the third dielectric materials. The conductive via structure at least penetrates the first and the second dielectric materials and is electrically connected to the first and the second external circuit layers to define a signal path. The conductive structures are electrically connected to each other and surround the first, the second and the third dielectric materials. The conductive structures are electrically connected to the first and the second external circuit layers to define a ground path surrounding the signal path.

公开(公告)号：US09932684B2

公开(公告)日：2018-04-03

申请号：US15220472

申请日：2016-07-27

Applicant: Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

Inventor： Matthew Thorseth ,  Zuhra Niazimbetova ,  Yi Qin ,  Julia Woertink ,  Joanna Dziewiszek ,  Erik Reddington ,  Mark Lefebvre

IPC: C25D3/38 ,  H01L23/00 ,  H05K3/06 ,  H05K1/11 ,  H05K3/40 ,  C25D7/12 ,  C25D5/02 ,  C25D7/00

CPC classification number: C25D3/38 ,  C25D5/022 ,  C25D7/00 ,  C25D7/123 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/05015 ,  H01L2224/11 ,  H01L2224/11472 ,  H01L2224/13014 ,  H01L2224/13147 ,  H05K1/111 ,  H05K3/064 ,  H05K3/4007 ,  H05K2201/09209 ,  H01L2924/00012

Abstract: Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of α-amino acids and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

公开(公告)号：US09820380B2

公开(公告)日：2017-11-14

申请号：US15444203

申请日：2017-02-27

Applicant: FUJIFILM Corporation

Inventor： Kensuke Katagiri ,  Shin Tajiri ,  Akihiko Hase

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/02 ,  G06F3/041

CPC classification number: H05K1/09 ,  G06F3/041 ,  G06F3/044 ,  G06F3/045 ,  G09F9/00 ,  H01B1/02 ,  H01L51/0021 ,  H01L51/5212 ,  H05K1/0296 ,  H05K3/027 ,  H05K3/10 ,  H05K2201/0364 ,  H05K2201/09209 ,  H05K2203/0502 ,  Y10T29/49155

Abstract: A transparent conductive film comprises a transparent substrate and a metal wiring portion formed thereon. A thin metal wire contained in an electrode portion in the metal wiring portion has a surface shape satisfying the condition of Ra2/Sm>0.01 μm and has a metal volume content of 35% or more. Ra represents an arithmetic average roughness in micrometers and is equal to or smaller than the thickness of a metal wiring located in a position where the surface roughness is measured. Sm represents an average distance between convex portions and is 0.01 μm or more.

公开(公告)号：US09820377B2

公开(公告)日：2017-11-14

申请号：US14947831

申请日：2015-11-20

Applicant: FUJIFILM CORPORATION

Inventor： Kensuke Katagiri ,  Shin Tajiri ,  Akihiko Hase

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/02 ,  G06F3/041 ,  G06F3/044 ,  G09F9/00 ,  H01B1/02 ,  H01L51/00 ,  G06F3/045 ,  H01L51/52

CPC classification number: H05K1/09 ,  G06F3/041 ,  G06F3/044 ,  G06F3/045 ,  G09F9/00 ,  H01B1/02 ,  H01L51/0021 ,  H01L51/5212 ,  H05K1/0296 ,  H05K3/027 ,  H05K3/10 ,  H05K2201/0364 ,  H05K2201/09209 ,  H05K2203/0502 ,  Y10T29/49155

Abstract: A transparent conductive film comprises a transparent substrate and a metal wiring portion formed thereon. A thin metal wire contained in an electrode portion in the metal wiring portion has a surface shape satisfying the condition of Ra2/Sm>0.01 μm and has a metal volume content of 35% or more. Ra represents an arithmetic average roughness in micrometers and is equal to or smaller than the thickness of a metal wiring located in a position where the surface roughness is measured. Sm represents an average distance between convex portions and is 0.01 μm or more.

公开(公告)号：US20170181287A1

公开(公告)日：2017-06-22

申请号：US15064016

申请日：2016-03-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jyun-Yuan Jhang ,  Ming-Fan Tsai ,  Ho-Chuan Lin ,  Ying-Wei Lu ,  Guang-Hwa Ma

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/185 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/552 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01Q1/2283 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q9/0407 ,  H05K1/0216 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09209

Abstract: An electronic package is provided, which includes a substrate and an antenna board structure disposed on the substrate. The antenna board structure has a first portion, a second portion and a partition portion between the first portion and the second portion. As such, current can be split into two paths so as to spread electromagnetic radiation, and thus produce electromagnetic radiation with a high bandwidth.

公开(公告)号：US20160163611A1

公开(公告)日：2016-06-09

申请号：US14558864

申请日：2014-12-03

Applicant: International Business Machines Corporation

Inventor： Edmund Blackshear ,  Shidong Li

IPC: H01L23/14 ,  B32B15/092 ,  B32B27/06 ,  H01L23/13 ,  B32B37/14 ,  B32B38/00 ,  H01L21/48 ,  B32B3/26 ,  B32B27/38

CPC classification number: H01L23/49833 ,  B32B3/08 ,  B32B3/10 ,  B32B3/266 ,  B32B5/16 ,  B32B7/02 ,  B32B15/092 ,  B32B15/20 ,  B32B27/04 ,  B32B27/20 ,  B32B27/38 ,  B32B37/02 ,  B32B37/182 ,  B32B38/0004 ,  B32B2250/05 ,  B32B2250/40 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2264/10 ,  B32B2264/101 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/734 ,  B32B2363/00 ,  B32B2457/00 ,  B32B2457/14 ,  H01L21/4803 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/0137 ,  H05K2201/0191 ,  H05K2201/0206 ,  H05K2201/0209 ,  H05K2201/09136 ,  H05K2201/09209 ,  H05K2201/0929 ,  H05K2203/06 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24298 ,  Y10T428/24314 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/25 ,  H01L2924/00

Abstract: A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.

Abstract translation: 一种用于接收半导体芯片的层叠基板。 包括层叠层叠以形成层压基板的层压层，每个层压层包括芯，其包括颗粒填充的环氧树脂和芯上的金属层。 至少一个层压层具有穿过金属层的径向切口，径向切口从至少一层压层的周边延伸到至少一层压层的中心。 径向切割仅穿过金属层，并且不切穿芯。

公开(公告)号：US20160081184A1

公开(公告)日：2016-03-17

申请号：US14947831

申请日：2015-11-20

Applicant: FUJIFILM CORPORATION

Inventor： Kensuke KATAGIRI ,  Shin TAJIRI ,  Akihiko HASE

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K1/09 ,  G06F3/041 ,  G06F3/044 ,  G06F3/045 ,  G09F9/00 ,  H01B1/02 ,  H01L51/0021 ,  H01L51/5212 ,  H05K1/0296 ,  H05K3/027 ,  H05K3/10 ,  H05K2201/0364 ,  H05K2201/09209 ,  H05K2203/0502 ,  Y10T29/49155

Abstract: A transparent conductive film comprises a transparent substrate and a metal wiring portion formed thereon. A thin metal wire contained in an electrode portion in the metal wiring portion has a surface shape satisfying the condition of Ra2/Sm>0.01 μm and has a metal volume content of 35% or more. Ra represents an arithmetic average roughness in micrometers and is equal to or smaller than the thickness of a metal wiring located in a position where the surface roughness is measured. Sm represents an average distance between convex portions and is 0.01 μm or more.

Abstract translation: 透明导电膜包括透明基板和形成在其上的金属布线部分。 包含在金属配线部的电极部的细金属丝具有满足Ra2 / Sm>0.01μm的条件的表面形状，金属体积含量为35％以上。 Ra表示以微米为单位的算术平均粗糙度，并且等于或小于位于测量表面粗糙度的位置的金属布线的厚度。 Sm表示凸部之间的平均距离，为0.01μm以上。

公开(公告)号：US09277642B2

公开(公告)日：2016-03-01

申请号：US14012216

申请日：2013-08-28

Applicant: Eastman Kodak Company

Inventor： Ronald Steven Cok

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一，第二和第三不同的邮票。 在基板上形成可固化的底部，连接层和顶层。 底层微通道印在中心区域和边缘区域的底层中，连接层微通道被压印在底层微通道上的边缘区域中的连接层中，边缘 微通道印在连接层微通道上的边缘区域的顶层中，顶层微通道印在中心区域的顶层中。 微线形成在每个微通道中。 中心区域的底层微线电连接到边缘区域中的边缘微线，并与顶层微线电隔离。

公开(公告)号：US09215798B2

公开(公告)日：2015-12-15

申请号：US14012173

申请日：2013-08-28

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H01B13/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channel(s) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供衬底，第一印模和不同的多级第二印模。 在基板上设置可固化的底层。 一个或多个底层微通道被印刷在可固化底层中，第一印模和底层微线形成在每个底层微通道中。 在固化的底层附近形成可固化的多层，并且与固化的底层接触。 第一和第二多层微通道和顶层微通道用多级第二印记印在可固化多层中。 两个底层微电线通过第一和第二多层微线电连接，并且顶层微线或两个顶层微线通过第一和第二多层微电子电连接 电线和底层微线。