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公开(公告)号：KR101901708B1
公开(公告)日：2018-09-28
申请号：KR1020170088853
申请日：2017-07-13
Applicant: 삼성전기주식회사
CPC classification number: H01G4/2325 , H01G4/012 , H01G4/30
Abstract: 본발명의일 실시예는유전층을사이에두고서로대향하는제1 및제2 내부전극을포함하는바디; 및상기바디의외측에배치되어, 상기제1 및제2 내부전극과각각전기적으로연결되는제1 및제2 외부전극;을포함하고, 상기제1 및제2 외부전극은, TiW, TiN 및 TaN 으로이루어진군에서선택되는어느하나또는이들의조합을포함하는제1 전극층; 및상기제1 전극층상에배치되는제2 전극층;을포함하는적층세라믹커패시터를제공한다.
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公开(公告)号：KR1020150012474A
公开(公告)日：2015-02-04
申请号：KR1020130088018
申请日：2013-07-25
Applicant: 삼성전기주식회사
IPC: H05K3/34
CPC classification number: H05K3/3457 , H05K1/111 , H05K3/388 , H05K2201/0338 , H05K2201/09663 , Y02P70/611
Abstract: 본 발명은 인쇄회로기판 및 그 제조방법에 관한 것으로, 더욱 상세하게는 인쇄회로기판에 실장되는 전자부품과 회로배선 사이의 신뢰성을 향상시킬 수 있는 인쇄회로기판 및 그 제조방법에 관한 것이다.
본 발명에 따른 인쇄회로기판은, 절연층; 상기 절연층 상에 형성된 금속패드; 상기 금속패드 상에 형성된 표면 처리층; 상기 표면 처리층 및 상기 절연층에 형성된 솔더층; 및 상기 솔더층과 상기 표면 처리층 사이에 형성되는 금속간 화합물층;을 포함한다.
또한 본 발명에 따른 인쇄회로기판은, 절연층; 상기 절연층 상에 형성된 금속 시드층; 상기 금속 시드층 상에 형성된 금속패드; 상기 금속패드 및 상기 금속 시드층에 형성된 표면 처리층; 상기 금속패드의 표면 처리층 및 상기 금속 시드층의 표면 처리층에 형성된 솔더층; 및 상기 솔더층과 상기 표면 처리층 사이에 형성되는 금속간 화합물층;을 포함한다.Abstract translation: 印刷电路板（PCB）及其制造方法技术领域本发明涉及印刷电路板（PCB）及其制造方法。 更具体地，本发明涉及能够提高电路线与安装在PCB上的电子部件之间的可靠性的PCB及其制造方法。 根据本发明的PCB包括绝缘层; 形成在所述绝缘层上的金属焊盘; 形成在所述金属垫上的表面处理层; 形成在表面处理层和绝缘层上的焊料层; 以及形成在焊料层和表面处理层之间的金属间复合层。 此外，根据本发明的PCB包括绝缘层; 形成在所述绝缘层上的金属籽晶层; 形成在金属籽晶层上的金属垫; 形成在所述金属焊盘和所述金属种子层上的表面处理层; 形成在金属焊盘的表面处理层和金属种子层的表面处理层上的焊料层; 和金属间复合层。
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公开(公告)号：KR1020140043955A
公开(公告)日：2014-04-14
申请号：KR1020120105298
申请日：2012-09-21
Applicant: 삼성전기주식회사
CPC classification number: B32B15/018 , B32B15/043 , C22C5/02 , C22C5/04 , C23C18/1651 , C23C18/1653 , C23C18/1844 , C23C18/42 , C23C18/44 , C23C18/54 , C23C28/021 , C23C28/023 , C25D5/10 , H01L24/00 , H05K3/244 , H05K2201/09472 , Y10T428/12396 , Y10T428/12514 , Y10T428/12868 , Y10T428/12875 , H01L24/81 , H01L23/12 , H01L24/11 , H01L2224/2746 , H01L2224/32225
Abstract: The present invention relates to an electrode pad, a printed circuit board using the same pad, and a method for manufacturing the printed circuit board. According to one embodiment of the present invention, the electrode pad includes a connection terminal part; a first plating layer including palladium phosphorus (Pd-P); and a second plating layer including palladium (Pd). According to one embodiment of the present invention, the first plating layer including palladium phosphorus (Pd-P) is formed on the connection terminal part. The second plating layer including palladium (Pd) is formed on the first plating layer.
Abstract translation: 本发明涉及电极焊盘，使用该焊盘的印刷电路板以及印刷电路板的制造方法。 根据本发明的一个实施例，电极焊盘包括连接端子部分; 包括钯磷（Pd-P）的第一镀层; 和包含钯（Pd）的第二镀层。 根据本发明的一个实施例，在连接端子部分上形成包括钯磷（Pd-P）的第一镀层。 包括钯（Pd）的第二镀层形成在第一镀层上。
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公开(公告)号：KR1020130046723A
公开(公告)日：2013-05-08
申请号：KR1020110111266
申请日：2011-10-28
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A manufacturing method of a printed circuit board having an NSMD(Non Solder Mask Defined) type is provided to remove a catalyst adhering to a film layer by coating and removing the film layer, thereby preventing a blurring phenomenon caused by the catalyst remaining on a substrate in processing a surface. CONSTITUTION: A base substrate is coated with a first film layer on which a first circuit pattern forming area is opened(S100). A first plating layer is formed in the base substrate coated with the first film layer(S102). The base substrate in which the first plating layer is formed is coated with a second film layer of which a second circuit pattern forming area is opened(S103). A circuit pattern is formed by forming a second plating layer in the first and second circuit pattern forming area(S105). The second film layer, the first plating layer and the first film layer are sequentially removed(S106,S107,S108). [Reference numerals] (AA) Start; (BB) End; (S100) Coat a first film layer on a base substrate; (S101) Open a first circuit pattern forming area by removing a part of the first film layer; (S102a) Adsorb a catalyst; (S102b) Form a first plating layer by plating metal; (S103) Coat a second film layer; (S104) Open a second circuit pattern forming area by removing a part of the second film layer; (S105) Form a second plating layer on first and second circuit patterns; (S106) Remove the second film layer; (S107) Etch the first plating layer; (S108) Remove the first film layer; (S109) Coat solder resist which part is removed; (S110) Process a surface
Abstract translation: 目的：提供具有NSMD（非焊接掩模定义）型的印刷电路板的制造方法，通过涂布和除去膜层来除去附着在膜层上的催化剂，从而防止由催化剂残留引起的模糊现象 处理表面的基板。 构成：基底衬底涂有第一电路图形形成区域打开的第一膜层（S100）。 在涂覆有第一膜层的基底基板中形成第一镀层（S102）。 其上形成有第一镀层的基底涂覆有打开第二电路图案形成区域的第二膜层（S103）。 通过在第一和第二电路图案形成区域中形成第二镀层形成电路图案（S105）。 依次去除第二膜层，第一镀层和第一膜层（S106，S107，S108）。 （附图标记）（AA）开始; （BB）结束; （S100）在基底基板上涂覆第一膜层; （S101）通过去除第一膜层的一部分来打开第一电路图案形成区域; （S102a）吸附催化剂; （S102b）通过电镀金属形成第一镀层; （S103）涂覆第二膜层; （S104）通过去除第二膜层的一部分来打开第二电路图案形成区域; （S105）在第一和第二电路图案上形成第二镀层; （S106）取出第二膜层; （S107）蚀刻第一镀层; （S108）拆下第一层膜; （S109）去除部分的涂覆阻焊剂; （S110）处理表面
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公开(公告)号：KR1020130001980A
公开(公告)日：2013-01-07
申请号：KR1020110062940
申请日：2011-06-28
Applicant: 삼성전기주식회사
CPC classification number: H05K1/0242 , B32B15/018 , C22C19/03 , C23C18/1651 , C23C18/32 , C23C18/54 , H01L2224/45144 , H01L2224/85444 , H05K1/0216 , H05K1/09 , H05K3/181 , H05K3/244 , H05K7/00 , H05K2201/0338 , H05K2201/0352 , H05K2203/072 , Y10T428/12889
Abstract: PURPOSE: An electroless plated layer of a printed circuit board and a method for preparing the same are provided to protect a copper layer by forming a plating layer. CONSTITUTION: An electroless plated layer is made of electroless nickel, palladium, and gold. The thickness of electroless nickel is 0.02-1 micrometer. The thickness of palladium is 0.01-0.3 micrometer. The thickness of a gold plating film is 0.01-0.5 micrometer. The electroless plated layer is connected to an exterior device in a wire bonding type and contains phosphorus.
Abstract translation: 目的：提供印刷电路板的无电镀层及其制备方法，以通过形成镀层来保护铜层。 构成：化学镀层由无电镍，钯和金制成。 化学镀镍的厚度为0.02-1微米。 钯的厚度为0.01-0.3微米。 镀金膜的厚度为0.01-0.5微米。 无电镀层以引线接合型连接到外部装置，并含有磷。
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Patent Agency Ranking
公开(公告)号：KR101055473B1
公开(公告)日：2011-08-08
申请号：KR1020090124707
申请日：2009-12-15
Applicant: 삼성전기주식회사
IPC: H05K3/46
CPC classification number: H05K3/4644 , H05K3/0097 , H05K2203/1536 , Y10T428/12681 , Y10T428/12701 , Y10T428/12708 , Y10T428/12736 , Y10T428/12785 , Y10T428/12792 , Y10T428/12903 , Y10T428/12944 , Y10T428/12986
Abstract: 본 발명은 기판 제조용 캐리어 부재 및 이를 이용한 기판의 제조방법에 관한 것으로, 본 발명에 따른 기판 제조용 캐리어 부재는 일면에 제1 금속층이 적층되고 타면에 제2 금속층이 적층된 2개의 절연층 및 2개의 상기 절연층에 각각 적층된 2개의 상기 제1 금속층을 서로 결합시키도록 2개의 상기 제1 금속층 사이에 형성되고 상기 제1 금속층보다 낮은 용융점을 갖는 제3 금속층을 포함하여 구성되며, 제3 금속층을 채용함으로써 가열하여 캐리어 부재를 분리할 수 있고, 이에 따라 캐리어 부재 분리시 기판의 사이즈가 변경되지 않아 기판과 제조설비 사이에 호환성을 유지할 수 있는 장점이 있다.
캐리어 부재, 주석, 동박적층판(CCL), 금속간화합물(intermetallic compound), 기판-
公开(公告)号：KR1020070075003A
公开(公告)日：2007-07-18
申请号：KR1020060003245
申请日：2006-01-11
Applicant: 삼성전기주식회사
IPC: G02F1/13357
CPC classification number: G02B6/0036 , G02B6/0068 , G02B6/0073 , G02F1/133615
Abstract: A light guiding plate is provided to secure excellent color reproducibility even with the small number of LEDs, by forming discontinuous patterns along concentric circles formed on a surface of the light guiding plate. A flat-shaped light guiding plate(100) includes an upper surface(106) and a lower surface facing each other, and lateral surfaces(108,112) formed between the upper surface and the lower surface. A plurality of patterns(104) are formed on the upper surface or the lower surface, wherein the patterns are disposed along plural concentric circles around a center of one edge or a center of a reference line parallel with the edge. The plural concentric circles are distanced from each other at the same interval. Respective patterns on each concentric circle are distanced from each other at a uniform interval. The farther the pattern is positioned from the center, the larger the size of the pattern is.
Abstract translation: 通过在形成于导光板的表面上的同心圆上形成不连续的图案，提供导光板，以便通过少量的LED来确保优异的颜色再现性。 扁平形状的导光板（100）包括上表面（106）和彼此面对的下表面以及形成在上表面和下表面之间的侧表面（108,112）。 多个图案（104）形成在上表面或下表面上，其中图案沿着与边缘平行的一个边缘的中心或参考线的中心的多个同心圆布置。 多个同心圆以相同的间隔相互间隔。 每个同心圆上的相应图案以均匀的间隔相互间隔开。 图案距离中心越远，图案的尺寸越大。
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公开(公告)号：KR1020140054792A
公开(公告)日：2014-05-09
申请号：KR1020120120723
申请日：2012-10-29
Applicant: 삼성전기주식회사
Abstract: The present invention relates to a capacitor comprising a first substrate, a first capacity unit formed on the first substrate; a protection layer formed on the first substrate; a second capacity unit formed on the protection layer; and a second substrate formed on the second capacity unit. More specifically, the first capacity unit comprises a first lower electrode, a first dielectric layer, and a first upper electrode and the second capacity unit comprises a second lower electrode, a second dielectric layer, and a second upper electrode.
Abstract translation: 本发明涉及一种电容器，包括：第一基板，形成在第一基板上的第一电容单元; 形成在所述第一基板上的保护层; 形成在保护层上的第二容量单元; 以及形成在第二容量单元上的第二衬底。 更具体地，第一容量单元包括第一下电极，第一电介质层和第一上电极，第二电容单元包括第二下电极，第二电介质层和第二上电极。
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公开(公告)号：KR1020140033700A
公开(公告)日：2014-03-19
申请号：KR1020120099857
申请日：2012-09-10
Applicant: 삼성전기주식회사
CPC classification number: H05K3/182 , H05K1/0298 , H05K3/244 , H05K3/3452 , H05K2201/0338 , H05K2201/099 , H05K2203/0577
Abstract: The present invention relates to a circuit board which comprises a circuit pattern formed on a board; a first solder resist layer formed on the circuit board; an electroless-plated layer formed on the circuit board with the opened first solder resist layer; and a second resist layer formed on the first solder resist layer, and a method for manufacturing the circuit board. According to an embodiment of the present invention, by comprising an additional solder resist layer on the plated layer finished with surface treatment, the area plated badly caused by the solder resist residue around the edge of existing solder resist layer or the lack of wetting can be covered. The under-cut part under the solder resist layer can be protected by forming an additional solder resist layer.
Abstract translation: 电路板技术领域本发明涉及一种电路板，其包括形成在电路板上的电路图案; 形成在电路板上的第一阻焊层; 在所述电路板上形成有开放的第一阻焊层的化学镀层; 以及形成在第一阻焊层上的第二抗蚀剂层，以及制造电路板的方法。 根据本发明的一个实施方案，通过在表面处理完成的镀层上包含另外的阻焊层，由现有阻焊层边缘周围的阻焊剂残留物所镀的区域或不能润湿的区域可以是 覆盖。 可以通过形成另外的阻焊层来保护阻焊层下的下切部分。
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公开(公告)号：KR1020140019175A
公开(公告)日：2014-02-14
申请号：KR1020120085825
申请日：2012-08-06
Applicant: 삼성전기주식회사
CPC classification number: C23C18/38 , C23C18/1655 , C23C18/40
Abstract: Provided in the present invention are a catalyst solution for electroless copper plating, a manufacturing method thereof, and an electroless plating method using the same. When performing electroless plating using a catalyst solution which compounds copper salt with an iodine compound, the catalyst solution has relatively low costs and high safety compared to the conventional palladium catalyst. In addition, when manufacturing a printed circuit board using the catalyst solution, residues do not exist after an etching process. Therefore, the catalyst solution can prevent insulation defects, or bridge defects of an electroless Ni/Au process in the final process, thereby improving the yield rate of products.
Abstract translation: 在本发明中提供了一种用于化学镀铜的催化剂溶液，其制造方法和使用其的化学镀方法。 当使用与碘化合物一起化合铜盐的催化剂溶液进行化学镀时，与常规的钯催化剂相比，催化剂溶液具有相对低的成本和高的安全性。 此外，当使用催化剂溶液制造印刷电路板时，在蚀刻工艺之后不存在残留物。 因此，催化剂溶液可以防止最终工艺中的无电Ni / Au工艺的绝缘缺陷或桥接缺陷，从而提高产品的产率。
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