公开(公告)号：KR1020110090585A

公开(公告)日：2011-08-10

申请号：KR1020100010457

申请日：2010-02-04

Applicant: 삼성전자주식회사

Inventor： 강필규 ,  배대록 ,  최길현 ,  이종명

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13

CPC classification number: H01L21/7624 ,  G02B6/02 ,  G02B6/12016 ,  G02B6/1221 ,  G02B6/131

Abstract: PURPOSE: A light input and output element of a photoelectric integrated circuit and a forming method thereof are provided to prevent the generation of thickness difference of a substrate in the same board or the different substrate and to control the step coverage which is generated in a coupling domain of optical waveguides in which the width are different. CONSTITUTION: A substrate(110) has a trench. An under-clad layer is provided within the trench and has the upper side lower than the surface of the substrate. The under-clad layer comprises silicon oxide. A core is separated from sidewalls of the trench and provided on the top of the under-clad layer and has the upper side which has same height with the surface of the substrate. The core comprises single crystal silicon. The single crystal silicon is formed by laser induction epitaxial growth way.

Abstract translation: 目的：提供光电集成电路的光输入输出元件及其形成方法，以防止在同一基板或不同基板上产生基板的厚度差异，并且控制在耦合中产生的台阶覆盖 其中宽度不同的光波导的区域。 构成：衬底（110）具有沟槽。 在沟槽内部设置有下覆层，并且其上侧比衬底的表面低。 下覆层包括氧化硅。 核心与沟槽的侧壁分离，并且设置在下包层的顶部上，并且具有与衬底的表面相同高度的上侧。 核心包括单晶硅。 单晶硅通过激光诱导外延生长方式形成。

公开(公告)号：KR1020100066783A

公开(公告)日：2010-06-18

申请号：KR1020080125251

申请日：2008-12-10

Applicant: 삼성전자주식회사

Inventor： 강필규 ,  배대록 ,  이종욱 ,  최승우 ,  손용훈 ,  강종혁 ,  김중호

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11578 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/02293 ,  H01L27/0688

Abstract: PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to remove a difference in a cross section corresponding to height by forming an active post through the patterning of a substrate before forming a gate. CONSTITUTION: An active post(106) is formed by patterning a bulk substrate. A charge trapping film is formed on the side of the active post. A plurality of gates(130a-130f) in contact with the active post is formed while interposing the charge trapping film. A semiconductor substrate is formed by etching the bulk substrate(102). A first joint area(108) is formed between the semiconductor substrate and the active post.

Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，通过在形成栅极之前通过图案化衬底形成活性柱来消除对应于高度的横截面的差异。 构成：通过图案化大块基板形成活性柱（106）。 在活性柱的一侧形成电荷捕获膜。 与活性柱接触的多个栅极（130a-130f）在插入电荷捕获膜的同时形成。 半导体衬底通过蚀刻大块衬底（102）形成。 第一接合区域（108）形成在半导体衬底和活性柱之间。

公开(公告)号：KR100837280B1

公开(公告)日：2008-06-11

申请号：KR1020070024094

申请日：2007-03-12

Applicant: 삼성전자주식회사

Inventor： 박영수 ,  김영남 ,  임영삼 ,  김기정 ,  강필규

IPC: H01L21/00

CPC classification number: H01L21/3221 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor device having a gettering region and a manufacturing method thereof are provided to improve integration density of the semiconductor device by minimizing a metal contamination of an IC formed on a semiconductor layer. A semiconductor device includes a semiconductor substrate(100), an insulation layer(150), a device semiconductor layer(200), and at least one gettering region(165). The insulation layer is arranged on the semiconductor substrate. The device semiconductor layer is arranged on the insulation layer. The gettering region includes plural sites for capturing metal elements in the device semiconductor layer. The gettering region is arranged in the insulation layer. The gettering region is arranged in a charge semiconductor pattern inside the insulation layer. The charge semiconductor pattern is contacted with a lower surface of the device semiconductor layer.

Abstract translation: 提供具有吸杂区域的半导体器件及其制造方法，以通过使形成在半导体层上的IC的金属污染最小化来提高半导体器件的集成密度。 半导体器件包括半导体衬底（100），绝缘层（150），器件半导体层（200）和至少一个吸杂区域（165）。 绝缘层设置在半导体衬底上。 器件半导体层布置在绝缘层上。 吸气区域包括用于捕获器件半导体层中的金属元素的多个位置。 吸气区域布置在绝缘层中。 吸气区域设置在绝缘层内部的电荷半导体图案中。 电荷半导体图案与器件半导体层的下表面接触。

公开(公告)号：KR100773359B1

公开(公告)日：2007-11-05

申请号：KR1020060114582

申请日：2006-11-20

Applicant: 삼성전자주식회사

Inventor： 이병찬 ,  손용훈 ,  정인수 ,  강필규

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/2683 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor having high mobility and a manufacturing method thereof are provided to suppress a leakage current at a hetero-junction between a source/drain region semiconductor layer and a semiconductor substrate by forming the source/drain region semiconductor layer in a recrystallized single crystal structure. Gate patterns(135a,135b,135c) are formed on a semiconductor substrate(100). A preliminary semiconductor layer is formed on the semiconductor substrate at both sides of the gate pattern. Source/drain semiconductor layers(155,156) are formed on the preliminary semiconductor layer by irradiating a laser beam on the preliminary semiconductor layer. A heterojunction is formed between the semiconductor substrate and the source/drain semiconductor layer. The source/drain semiconductor layer is formed in a recrystallized single crystal structure.

Abstract translation: 提供具有高迁移率的晶体管及其制造方法，以通过在再结晶单晶结构中形成源极/漏极区半导体层来抑制源/漏区半导体层和半导体衬底之间的异质结处的漏电流。 栅极图案（135a，135b，135c）形成在半导体衬底（100）上。 在栅极图案的两侧在半导体衬底上形成初步半导体层。 通过在初级半导体层上照射激光来在初级半导体层上形成源极/漏极半导体层（155,156）。 在半导体衬底和源极/漏极半导体层之间形成异质结。 源极/漏极半导体层以再结晶单晶结构形成。