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公开(公告)号：KR1020130135049A
公开(公告)日：2013-12-10
申请号：KR1020130040094
申请日：2013-04-11
Applicant: 한국전자통신연구원
IPC: H04B10/572 , H04B10/548 , H04B10/11
CPC classification number: H04B10/572 , H04B10/11 , H04B10/548 , H04B2210/25
Abstract: Disclosed is an interconnection apparatus using terahertz wave and a method thereof. According to the present invention, the interconnection apparatus using terahertz wave includes a first terahertz wave generation part generation a first transmission terahertz wave of the first center frequency; a second terahertz wave generation part generation a second transmission terahertz wave of the first center frequency; a first terahertz wave detection part detecting the first transmission terahertz wave corresponding to a first reception terahertz wave; and a second terahertz wave detection part detecting the second transmission terahertz wave corresponding to a second reception terahertz wave. [Reference numerals] (111,BB) First terahertz wave generation part;(112,AA) First terahertz wave detection part;(121,DD) Second terahertz wave generation part;(122,CC) Second terahertz wave detection part
Abstract translation: 公开了使用太赫兹波的互连装置及其方法。 根据本发明，使用太赫兹波的互连装置包括第一太赫兹波产生部分产生第一中心频率的第一传输太赫兹波; 第二太赫兹波产生部分产生第一中心频率的第二传输太赫兹波; 检测对应于第一接收太赫兹波的第一传输太赫兹波的第一太赫兹波检测部分; 以及第二太赫波检测部分，检测对应于第二接收太赫兹波的第二传输太赫兹波。 （111，BB）第一太赫波生成部;（112AA）第一太赫兹波检测部;（121DD）第二太赫波生成部;（122，CC）第二太赫兹波检测部
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公开(公告)号：KR101070409B1
公开(公告)日：2011-10-06
申请号：KR1020100074715
申请日：2010-08-02
Applicant: 한국전자통신연구원
CPC classification number: G02F1/025 , G02F1/2257 , G02F2001/212 , G02F2201/12 , G02F2202/105
Abstract: Provided is a Mach-Zehnder modulator. The Mach-Zehnder modulator comprises an input wave guide and an output wave guide arranged on a substrate, a first branch wave guide and a second branch wave guide connected in parallel between the input and output wave guides, and a connecting region configured to connect the first branch wave guide and the second branch wave guide. Each of the first and second branch wave guides comprises first doped regions doped with a first dopant and second doped regions doped with a second dopant having different conductivity from the first dopant, and the connecting region is doped with the first dopant and arranged between the first regions of the first and second branch wave guides.
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公开(公告)号：KR1020100066842A
公开(公告)日：2010-06-18
申请号：KR1020080125330
申请日：2008-12-10
Applicant: 한국전자통신연구원
IPC: H01L31/00 , H01L29/868
CPC classification number: G02F1/025 , G02F2001/0156 , G02F2201/063 , G02F2201/12 , G02F2202/105 , G02F2202/32
Abstract: PURPOSE: An optical loss modulator and a method for manufacturing the same are provided to reduce the cross section of the optical loss modulator by changing the absorption rate of an intrinsic region. CONSTITUTION: An insulating layer(12) is formed on a substrate(11). A waveguide(16) with a P-I-N diode structure is formed on the insulating layer. The absorption rate of the intrinsic region(15) of the P-I-N diode is changed in a modulation operation of a light inputted to the waveguide. The P-I-N diode includes the intrinsic region, the P-type region(13) of the intrinsic region, and the N type region(14) of the intrinsic region. The waveguide enhances the absorption rate of the intrinsic region by slowing the progressing speed of the light.
Abstract translation: 目的：提供光损耗调制器及其制造方法，以通过改变本征区域的吸收率来减小光损耗调制器的横截面。 构成：在基板（11）上形成绝缘层（12）。 在绝缘层上形成具有P-I-N二极管结构的波导（16）。 在输入到波导的光的调制操作中，P-I-N二极管的本征区域（15）的吸收率发生变化。 P-I-N二极管包括本征区域，本征区域的P型区域（13）和本征区域的N型区域（14）。 波导通过减慢光的进行速度来增强本征区域的吸收率。
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公开(公告)号：KR100937591B1
公开(公告)日：2010-01-20
申请号：KR1020070132339
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: H01L31/12
CPC classification number: G02F1/01708 , B82Y20/00 , G02F1/025 , G02F2001/0152 , G02F2201/302 , G02F2201/34 , G02F2203/02
Abstract: 반도체 광전 집적회로 및 그 형성 방법을 제공한다. 이 반도체 광전 집적회로는 기판 상에 배치되고 입력단 및 출력단을 포함하는 광도파로, 광도파로 상에 형성된 광 격자, 및 광 격자 상에 배치된 광 능동 소자를 포함한다.
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公开(公告)号：KR1020090064951A
公开(公告)日：2009-06-22
申请号：KR1020070132339
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: H01L31/12
CPC classification number: G02F1/01708 , B82Y20/00 , G02F1/025 , G02F2001/0152 , G02F2201/302 , G02F2201/34 , G02F2203/02
Abstract: A semiconductor optoelectronic integrated circuit and a forming method thereof are provided to increase a degree of integration by arranging an optical active element on an optical grating of an optical waveguide. A semiconductor optoelectronic integrated circuit includes an optical waveguide(105), an optical grating(107), and an optical active element. The optical waveguide is arranged on a substrate. The optical waveguide includes an input terminal and an output terminal. The optical grating is formed on the optical waveguide. The optical active element is formed on the optical grating. The optical active element receives an optical signal from the optical waveguide through the optical grating. The optical active element modulates the received optical signal.
Abstract translation: 提供半导体光电集成电路及其形成方法，以通过将光学有源元件布置在光波导的光栅上来增加集成度。 半导体光电集成电路包括光波导（105），光栅（107）和光有源元件。 光波导布置在基板上。 光波导包括输入端子和输出端子。 光栅形成在光波导上。 光学有源元件形成在光栅上。 光学有源元件通过光栅从光波导接收光信号。 光学有源元件调制接收到的光信号。
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Patent Agency Ranking
公开(公告)号：KR100494225B1
公开(公告)日：2005-06-13
申请号：KR1020030029440
申请日：2003-05-09
Applicant: 한국전자통신연구원
IPC: H01S5/32
Abstract: 본 발명은 광소자 및 광소자의 제조 방법에 관한 것으로, 능동 도파로와 수동 도파로가 집적된 광소자에 있어서, 수동 도파로에 도핑되지 않은 클래딩막을 형성함으로써, 수동 도파로의 광 도파 손실을 줄일 수 있고, 능동 도파로의 전류 누설을 방지하기 위한 별도의 패시베이션막 형성공정을 생략할 수 있는 광소자 및 광소자의 제조 방법을 제공한다.
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公开(公告)号：KR100471381B1
公开(公告)日：2005-03-10
申请号：KR1020020083055
申请日：2002-12-24
Applicant: 한국전자통신연구원
IPC: G02B6/12
Abstract: 본 발명은 능동 광소자와 수동 광소자의 집적 방법 및 그 소자에 관한 것으로, 한 기판에 서로 다른 수직 층 구조를 가지면서 다른 형태의 도파로 들이 집적된 능동 광소자와 수동 광소자의 집적 방법에 있어서, 능동 소자의 베리드 리지(buried ridge) 도파로 중심부를 식각할 때 베리드 리지와 연결된 수동 도파로 끝에 스트립 로디드(strip loaded) 형태로 변화시킬 수 있는 테이퍼를 형성하는 단계, 테이퍼를 재성장으로 덮는 단계 및 베리드 리지 도파로의 끝에 있는 테이퍼와 정렬하여 테이퍼로 끝나는 스트립 로디드 형태의 도파로를 식각으로 형성하는 단계를 포함한다. 따라서, 능동 소자에 사용되는 베리드 리지(buried ridge) 도파로와 수동 소자에 사용되는 리지(ridge) 또는 스트립 로디드(strip loaded) 도파로의 제작 공정이 분리되어 집접화된 소자의 제작에서 개별 도파로의 최적화된 제작 공정을 사용할 수 있다.
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公开(公告)号：KR100425588B1
公开(公告)日：2004-04-01
申请号：KR1020020008750
申请日：2002-02-19
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A method for fabricating an optical integrated circuit is provided to reduce the quantity of an etch byproduct and prevent an incomplete cleaving phenomenon by selectively wet-etching the second clad layer and by dry-etching the first clad layer, a core layer and a substrate. CONSTITUTION: An active device region and a passive device region are defined in a compound substrate(100). The core layer(105a,105b) and the first clad layer(110) are sequentially stacked on the compound substrate. An etch stopper(115) is formed on the first clad layer in the passive device region. A mask pattern for forming a waveguide is formed on the active device region and the passive device region. The passive device region is covered with the first passivation layer. A predetermined thickness of the first clad layer, the core layer and the compound substrate is etched to form an active device waveguide(130) by using the mask pattern in the exposed active device region. The first passivation layer is removed. The second clad layer is formed on the resultant structure. The active device region is covered with the second passivation layer. The second clad layer is wet-etched to expose the mask pattern in the passive device region. The etch stopper is wet-etched to have the type of the mask pattern in the passive device region. The first clad layer, the core layer and the compound substrate are dry-etched by a predetermined thickness to have the mask pattern in the passive device region so that an active device waveguide is formed.
Abstract translation: 目的：提供一种用于制造光学集成电路的方法，以通过选择性地湿法腐蚀第二覆盖层并且通过干法蚀刻第一覆盖层，芯层和第二覆盖层来减少蚀刻副产物的量并且防止不完全裂开现象 基质。 构成：有源器件区域和无源器件区域被限定在复合衬底（100）中。 芯层（105a，105b）和第一覆层（110）顺序堆叠在复合基板上。 在无源器件区域中的第一覆盖层上形成蚀刻阻挡层（115）。 用于形成波导的掩模图案形成在有源器件区域和无源器件区域上。 无源器件区域被第一钝化层覆盖。 通过使用暴露的有源器件区域中的掩模图案来蚀刻预定厚度的第一覆层，核心层和复合衬底以形成有源器件波导（130）。 第一钝化层被去除。 在所得到的结构上形成第二包层。 有源器件区域被第二钝化层覆盖。 湿蚀刻第二覆层以暴露无源器件区域中的掩模图案。 蚀刻停止层被湿蚀刻以具有无源器件区域中的掩模图案的类型。 第一覆盖层，核心层和化合物基板被干蚀刻预定厚度，以在无源器件区域中具有掩模图案，从而形成有源器件波导。
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公开(公告)号：KR100413527B1
公开(公告)日：2004-01-03
申请号：KR1020020005204
申请日：2002-01-29
Applicant: 한국전자통신연구원
IPC: G02B6/13
CPC classification number: H01S5/026 , H01S5/0265
Abstract: A method of fabricating a monolithic integrated semiconductor photonic device is provided. In this method, it is possible to remarkably reduce an optical loss in a passive waveguide by forming a non-doped clad layer around a passive layer. Thus, the passive waveguide can be effectively coupled with an active waveguide. Further, a current confinement layer is formed around an active layer, using the non-doped clad layer. Therefore, an expensive tool such as an ion implanter is not required, thereby decreasing manufacturing costs.
Abstract translation: 提供了一种制造单片集成半导体光子器件的方法。 在该方法中，通过在无源层周围形成非掺杂包层，可以显着降低无源波导中的光损耗。 因此，无源波导可以有效地与有源波导耦合。 此外，使用非掺杂包层在有源层周围形成电流限制层。 因此，不需要昂贵的工具如离子注入机，从而降低了制造成本。
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公开(公告)号：KR1020030069275A
公开(公告)日：2003-08-27
申请号：KR1020020008750
申请日：2002-02-19
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A method for fabricating an optical integrated circuit is provided to reduce the quantity of an etch byproduct and prevent an incomplete cleaving phenomenon by selectively wet-etching the second clad layer and by dry-etching the first clad layer, a core layer and a substrate. CONSTITUTION: An active device region and a passive device region are defined in a compound substrate(100). The core layer(105a,105b) and the first clad layer(110) are sequentially stacked on the compound substrate. An etch stopper(115) is formed on the first clad layer in the passive device region. A mask pattern for forming a waveguide is formed on the active device region and the passive device region. The passive device region is covered with the first passivation layer. A predetermined thickness of the first clad layer, the core layer and the compound substrate is etched to form an active device waveguide(130) by using the mask pattern in the exposed active device region. The first passivation layer is removed. The second clad layer is formed on the resultant structure. The active device region is covered with the second passivation layer. The second clad layer is wet-etched to expose the mask pattern in the passive device region. The etch stopper is wet-etched to have the type of the mask pattern in the passive device region. The first clad layer, the core layer and the compound substrate are dry-etched by a predetermined thickness to have the mask pattern in the passive device region so that an active device waveguide is formed.
Abstract translation: 目的：提供一种用于制造光学集成电路的方法，以减少蚀刻副产物的量，并通过选择性湿蚀刻第二包覆层来防止不完全的裂开现象，并且通过干蚀刻第一包覆层，芯层和 基质。 构成：在复合衬底（100）中限定有源器件区域和无源器件区域。 核心层（105a，105b）和第一覆盖层（110）依次层叠在复合基板上。 在无源器件区域中的第一覆盖层上形成蚀刻停止器（115）。 在有源器件区域和无源器件区域上形成用于形成波导的掩模图案。 无源器件区域被第一钝化层覆盖。 通过使用暴露的有源器件区域中的掩模图案来蚀刻第一覆盖层，芯层和复合衬底的预定厚度以形成有源器件波导（130）。 去除第一钝化层。 在所得结构上形成第二覆层。 有源器件区域被第二钝化层覆盖。 湿蚀刻第二覆盖层以暴露无源器件区域中的掩模图案。 蚀刻停止器被湿式蚀刻以在无源器件区域中具有掩模图案的类型。 将第一包覆层，芯层和复合衬底干蚀刻预定厚度以在无源器件区域中具有掩模图案，从而形成有源器件波导。
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