公开(公告)号：KR100450761B1

公开(公告)日：2004-10-01

申请号：KR1020020055995

申请日：2002-09-14

Applicant: 한국전자통신연구원

Inventor： 정중희 ,  황치선 ,  송윤호 ,  이진호

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0465 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: An active matrix organic light emitting diode display panel circuit capable of reducing current and brightness nonuniformities between pixels by including a threshold voltage compensation circuit block between a data line and the pixels is provided. The threshold voltage of a video signal loaded in a data line is compensated for while the video signal passes through the threshold voltage compensation circuit block and then provided to a driving transistor of the pixels. One threshold voltage compensation circuit block is connected commonly to a plurality of pixels, rather than be connected to every pixel, so that threshold voltage compensation can be achieved for high-quality, large-sized displays, without increasing the number of transistors for the pixels.

Abstract translation: 提供了一种有源矩阵有机发光二极管显示面板电路，其通过在数据线和像素之间包括阈值电压补偿电路块能够减小像素之间的电流和亮度不均匀性。 加载在数据线中的视频信号的阈值电压在视频信号通过阈值电压补偿电路块时被补偿，然后被提供给像素的驱动晶体管。 一个阈值电压补偿电路块被共同连接到多个像素，而不是连接到每个像素，使得可以实现用于高质量大尺寸显示器的阈值电压补偿，而不增加用于像素的晶体管的数量 。

公开(公告)号：KR100426495B1

公开(公告)日：2004-04-14

申请号：KR1020010086832

申请日：2001-12-28

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  윤용선 ,  안성덕 ,  송윤호 ,  이진호 ,  조경익

IPC: H01L27/102 ,  B82Y40/00

CPC classification number: H01L51/0504 ,  B82Y10/00 ,  H01L51/0048

Abstract: The present invention relates to a semiconductor device using a single carbon nanotube and a method of manufacturing the same. In a process of manufacturing a bipolar transistor using a p-n junction, a given region of a single carbon nanotube of a N type is exposed by means of a common semiconductor manufacturing process and the exposed portion of a carbon nanotube of a P type is then made to be a carbon a single carbon nanotube of a N type by means of a doping process, thus forming a P-N-P or N-P-N bipolar transistor. Therefore, the present invention can improve the integration degree and the operating speed of the device.

Abstract translation: 本发明涉及使用单个碳纳米管的半导体器件及其制造方法。 在使用pn结制造双极晶体管的过程中，通过共同的半导体制造工艺暴露N型单个碳纳米管的给定区域，然后制成P型碳纳米管的暴露部分 通过掺杂工艺成为N型单碳纳米管的碳，从而形成PNP或NPN双极晶体管。 因此，本发明可以提高装置的集成度和运行速度。

公开(公告)号：KR1020040026380A

公开(公告)日：2004-03-31

申请号：KR1020020057829

申请日：2002-09-24

Applicant: 한국전자통신연구원

Inventor： 김용해 ,  송윤호 ,  고영욱 ,  정중희 ,  손충용 ,  이진호

IPC: H01L29/786

Abstract: PURPOSE: A method for fabricating a display pixel with a two-story capacitor is provided to reduce the area of pixel occupied by a capacitor by using a two-story capacitor instead of a single-story capacitor. CONSTITUTION: An active layer(200) is formed on a substrate. A gate oxide layer(202), a gate layer(204) and a capping layer(206) are sequentially deposited on the active layer. The gate layer and the capping layer are etched to form a gate. A spacer is formed on the side surface of the gate. An ion implantation process is performed on the upper surface of the resultant structure. A conductive layer is deposited on the resultant structure to form the capacitor between the conductive layer and the gate and between the gate and the active layer.

Abstract translation: 目的：提供一种用于制造具有两层电容器的显示像素的方法，以通过使用二层电容器而不是单层电容器来减小由电容器占据的像素的面积。 构成：在衬底上形成有源层（200）。 栅极氧化物层（202），栅极层（204）和覆盖层（206）依次沉积在有源层上。 蚀刻栅极层和覆盖层以形成栅极。 在栅极的侧表面上形成间隔物。 在所得结构的上表面上进行离子注入工艺。 导电层沉积在所得结构上以在导电层和栅极之间以及栅极和有源层之间形成电容器。

公开(公告)号：KR100422808B1

公开(公告)日：2004-03-12

申请号：KR1020000086752

申请日：2000-12-30

Applicant: 한국전자통신연구원

Inventor： 황치선 ,  송윤호 ,  이진호 ,  조경익

IPC: H01L21/336

Abstract: PURPOSE: A fabrication method of TFTs(Thin Film Transistors) is provided to improve an operational characteristic, a manufacturing time, and a manufacturing cost by forming a thin active layer without a damage. CONSTITUTION: After forming a gate electrode(32) on a substrate(31), an isolating layer(33), an active layer(34) and an n+ doped layer(35) are sequentially and continuously formed. Then, a pattern is formed to enclose the upper portion of the gate electrode(32) by selectively etching the n+ doped layer(35) and the active layer(34). After depositing a metal layer(36) on the entire surface of the resultant structure, a source and a drain are formed on the resultant structure with a defined interval each other by selectively removing the metal layer(36). Then, the active layer(34) is partially exposed without a damage by selectively etching the n+ doped layer(35) using a high etch selectivity rate of the active layer(34).

Abstract translation: 目的：提供TFT（薄膜晶体管）的制造方法以通过形成薄的有源层而没有损坏来改善操作特性，制造时间和制造成本。 构成：在衬底（31）上形成栅电极（32）之后，顺序连续形成隔离层（33），有源层（34）和n +掺杂层（35）。 然后，通过选择性地蚀刻n +掺杂层（35）和有源层（34），形成图案以包围栅电极（32）的上部。 在所得结构的整个表面上沉积金属层（36）之后，通过选择性地去除金属层（36），在所得结构上以确定的间隔形成源极和漏极。 然后，通过使用有源层（34）的高蚀刻选择率选择性地蚀刻n +掺杂层（35），使有源层（34）部分暴露而没有损坏。

公开(公告)号：KR1020030062508A

公开(公告)日：2003-07-28

申请号：KR1020020002738

申请日：2002-01-17

Applicant: 한국전자통신연구원

Inventor： 정중희 ,  송윤호 ,  황치선 ,  이진호 ,  조경익

IPC: H01J1/30

Abstract: PURPOSE: A high brightness field emission display is provided to achieve improved field emission characteristics by lowering the drive voltage of field emitter and lengthening the scanning time. CONSTITUTION: A field emission display comprises pixels arranged into a matrix shape on a glass substrate. Each of pixels includes a ferroelectric transistor(200) formed on the glass substrate; and a thin film type field emitter(100) formed in the vicinity of the ferroelectric transistor. The ferroelectric transistor includes a band type gate; a ferroelectric film formed on the gate; a floating gate formed in parallel with the gate; an amorphous silicon channel formed by inserting an insulation film on the floating gate; a source and a drain formed on the amorphous silicon channel; and a source electrode and a drain electrode for connecting the source and the drain to an external terminal.

Abstract translation: 目的：提供高亮度场致发射显示器，通过降低场发射器的驱动电压和延长扫描时间来实现改进的场致发射特性。 构成：场致发射显示器包括在玻璃基板上排列成矩阵形状的像素。 每个像素包括形成在玻璃基板上的铁电晶体管（200） 以及形成在铁电晶体管附近的薄膜型场致发射体（100）。 铁电晶体管包括带状栅极; 栅极上形成的铁电膜; 与栅极平行形成的浮动栅极; 通过在浮动栅极上插入绝缘膜形成的非晶硅沟道; 形成在非晶硅沟道上的源极和漏极; 以及用于将源极和漏极连接到外部端子的源电极和漏电极。

公开(公告)号：KR100392362B1

公开(公告)日：2003-07-22

申请号：KR1020000086556

申请日：2000-12-30

Applicant: 한국전자통신연구원

Inventor： 황치선 ,  송윤호 ,  김도형 ,  이진호 ,  조경익

IPC: H01L21/3063

Abstract: PURPOSE: A selective etch method of silicon is provided to perform a wet etch having a good etch selectivity between a doped silicon thin film and an undoped silicon thin film. CONSTITUTION: An undoped silicon thin film(22) and a doped silicon thin film(23) are stacked on a defined process completed structure(21). Then, a mask pattern(24) is formed by selectively etching a photoresist or a metal having a wet etch selectivity with a polysilicon. Then, the doped silicon thin film(23) is selectively removed by a wet etching using the mask pattern(24). At this time, the wet etching is performed using a mixed solution made of HF, a nitric acid and an acetic acid or another mixed solution made of the HF, the nit acid and water. The mixed solution oxidizes a silicon thin film using the nitric acid and simultaneously etches an oxide using the HF.

Abstract translation: 目的：提供硅的选择性蚀刻方法以在掺杂硅薄膜和未掺杂硅薄膜之间执行具有良好蚀刻选择性的湿法蚀刻。 构成：将未掺杂的硅薄膜（22）和掺杂硅薄膜（23）堆叠在限定的加工完成结构（21）上。 然后，通过用多晶硅选择性地蚀刻具有湿法蚀刻选择性的光致抗蚀剂或金属，形成掩模图案（24）。 然后，使用掩模图案（24）通过湿法蚀刻选择性地去除掺杂硅薄膜（23）。 此时，使用由HF，硝酸和乙酸制成的混合溶液或由HF，硝酸和水制成的另一种混合溶液进行湿法蚀刻。 混合溶液使用硝酸氧化硅薄膜并且同时使用HF蚀刻氧化物。

公开(公告)号：KR1020030056571A

公开(公告)日：2003-07-04

申请号：KR1020010086833

申请日：2001-12-28

Applicant: 한국전자통신연구원

Inventor： 황치선 ,  송윤호 ,  이진호 ,  조경익

IPC: H01J1/30

CPC classification number: H01J29/96 ,  H01J1/46 ,  H01J3/021 ,  H01J29/02 ,  H01J29/467 ,  H01J31/127 ,  H01J2329/92 ,  H01L27/12 ,  H01L29/78669

Abstract: PURPOSE: A field emission display is provided to prevent the generation of the leakage current between a gate electrode and an emitter by connecting a resistor to the gate electrode. CONSTITUTION: A field emission display includes a gate electrode(202), an emitter(204), and an anode(207). The field emission display includes a resistor(209) connected to the gate electrode in order to intercept the leakage current between the gate electrode and the emitter. The resistor is formed with a metal wire having a large resistant value. The metal wire includes the first metal wire and the second metal wire. The second metal wire is adhered to both ends of the first metal wire. A resistant value of the second metal wire is smaller than the resistant value of the first metal wire.

Abstract translation: 目的：提供场发射显示器，以通过将电阻器连接到栅极电极来防止在栅电极和发射极之间产生漏电流。 构成：场发射显示器包括栅电极（202），发射极（204）和阳极（207）。 场发射显示器包括连接到栅电极的电阻器（209），以便截取栅电极和发射极之间的漏电流。 电阻器由具有大电阻值的金属线形成。 金属线包括第一金属线和第二金属线。 第二金属线粘附到第一金属线的两端。 第二金属线的电阻值小于第一金属线的电阻值。

公开(公告)号：KR1020030042656A

公开(公告)日：2003-06-02

申请号：KR1020010073394

申请日：2001-11-23

Applicant: 한국전자통신연구원

Inventor： 김봉철 ,  송윤호 ,  조영래 ,  이진호 ,  조경익

IPC: H01J1/30 ,  C01B31/02 ,  B82Y40/00

Abstract: PURPOSE: A method of fabricating a field emission display is provided to heighten the emission efficiency of the emitter by forming the carbon nanotube in the emitter vertical to the substrate. CONSTITUTION: In a method of fabricating a field emission display, an anode electrode(8) and a phosphor layer(7) are sequentially formed on the entire surface of a front substrate(2). A cathode electrode(3) is formed on the surface of a rear substrate(1). A carbon nanotube resin is coated onto the cathode electrode, and heat-treated to form an emitter(10). The front and the rear substrates are sealed to each other. After the formation of the cathode electrode, an insulating layer(5) is formed on the cathode electrode, and a gate electrode(6) is formed on the insulating layer. The carbon nanotube resin contains binder, conductive powder, and carbon nanotube.

Abstract translation: 目的：提供一种制造场发射显示器的方法，以通过在垂直于衬底的发射体中形成碳纳米管来提高发射器的发射效率。 构成：在制造场发射显示器的方法中，在前基板（2）的整个表面上依次形成阳极电极（8）和荧光体层（7）。 在后基板（1）的表面上形成阴极电极（3）。 将碳纳米管树脂涂覆到阴极上，进行热处理以形成发射体（10）。 前基板和后基板彼此密封。 在阴极电极形成之后，在阴极上形成绝缘层（5），在绝缘层上形成栅电极（6）。 碳纳米管树脂含有粘合剂，导电粉末和碳纳米管。

公开(公告)号：KR1020020091620A

公开(公告)日：2002-12-06

申请号：KR1020010030447

申请日：2001-05-31

Applicant: 한국전자통신연구원

Inventor： 송윤호 ,  김홍주 ,  이진호 ,  조경익

IPC: H01J1/30 ,  C01B31/02

Abstract: PURPOSE: A field emission display device is provided to improve a yield of the field emission display device by forming a TFT(Thin Film Transistor) having an off-set region and a field emitter in the inside of dot pixels of a lower substrate. CONSTITUTION: A channel(402) of a TFT is formed on a part of an organic substrate(401). The channel(402) is formed with undoped poly-crystalline silicon. A source(403) and a drain(404) are formed on both sides of the channel(402). The source(403) and the drain(404) are formed with doped poly-crystalline silicon. A gate insulating layer(405) is formed on the substrate(401) including the channel(402), the source(403), and the drain(404) of the TFT. The gate insulating layer(405) is formed an oxide layer. A gate(406) is formed on a part of the gate insulating layer(405). The gate(406) is formed with metal or doped poly-crystalline silicon. The gate(406) is vertically overlapped with a part of the source(403) and the channel(402). The gate(406) is not overlapped with the drain(404). An interlayer dielectric(407) is formed on the substrate(401). A drain electrode(408) is formed on a part of the interlayer dielectric(407). A buffer electrode(409) is formed on a part of the drain electrode(408). A field emission layer(410) is formed on formed on a part of the buffer electrode(409). A transparent electrode(422) is formed on a glass substrate(421). A plurality of dot pixels including fluorescent materials(423) are formed on the transparent electrode(422).

Abstract translation: 目的：提供场致发射显示装置，通过在下基板的点像素的内部形成具有偏移区域和场发射极的TFT（薄膜晶体管）来提高场致发射显示装置的产量。 构成：TFT的通道（402）形成在有机基板（401）的一部分上。 通道（402）由未掺杂的多晶硅形成。 源（403）和漏极（404）形成在通道（402）的两侧。 源极（403）和漏极（404）由掺杂的多晶硅形成。 在包括TFT的沟道（402），源极（403）和漏极（404）的衬底（401）上形成栅极绝缘层（405）。 栅极绝缘层（405）形成氧化物层。 栅极（406）形成在栅极绝缘层（405）的一部分上。 栅极（406）由金属或掺杂的多晶硅形成。 门（406）与源（403）和通道（402）的一部分垂直重叠。 栅极（406）不与漏极（404）重叠。 在基板（401）上形成层间电介质（407）。 漏极电极（408）形成在层间电介质（407）的一部分上。 缓冲电极（409）形成在漏电极（408）的一部分上。 形成在缓冲电极（409）的一部分上的场致发射层（410）。 透明电极（422）形成在玻璃基板（421）上。 在透明电极（422）上形成包括荧光材料（423）的多个点像素。

公开(公告)号：KR1020020008439A

公开(公告)日：2002-01-31

申请号：KR1020000041574

申请日：2000-07-20

Applicant: 한국전자통신연구원

Inventor： 조영래 ,  이진호 ,  정문연 ,  강승열 ,  송윤호 ,  조경익

IPC: H01J1/30

Abstract: PURPOSE: A vacuum packaging method of an electronic device, and a sealant planarization apparatus for vacuum packaging are provided, which can control a thickness of a frit glass easily and can arrange an upper plate and a lower plate easily, and can reduce a damage of a glass substrate during the vacuum packaging using the frit glass. CONSTITUTION: A planarization apparatus for a vacuum packaging of an electronic device performs a vacuum packaging of an upper plate(520) and a lower plate using a frit glass(530). The planarization apparatus includes an installation unit where a substrate coated with the frit glass is installed, and a pressing unit(580) pressing the frit glass coated on the above substrate as doing a relative movement as to the installation unit, and a control unit(595) controlling the degree of pressing of the frit glass by controlling a gap between the installation unit and the pressing unit. The pressing unit controls the thickness as planarizing the frit glass by pressing the frit glass continuously.

Abstract translation: 目的：提供电子装置的真空包装方法以及用于真空包装的密封剂平面化装置，其可以容易地控制熔结玻璃的厚度，并且可以容易地布置上板和下板，并且可以减少 在使用熔结玻璃的真空包装期间的玻璃基板。 构成：用于电子设备的真空包装的平面化装置使用熔结玻璃（530）进行上板（520）和下板的真空包装。 平面化装置包括安装有被熔敷了玻璃料的基板的安装单元和对安装单元进行相对移动而将涂覆在上述基板上的玻璃料玻璃按压的按压单元（580），以及控制单元 595）通过控制安装单元和按压单元之间的间隙来控制熔结玻璃的压制程度。 压制单元通过连续挤压玻璃料玻璃来控制将玻璃料平坦化的厚度。