公开(公告)号：KR1020110025500A

公开(公告)日：2011-03-10

申请号：KR1020090083600

申请日：2009-09-04

Applicant: 한국전자통신연구원

Inventor： 안호균 ,  임종원 ,  윤형섭 ,  장우진 ,  김해천

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/8128 ,  H01L29/42316 ,  H01L29/66863 ,  H01L21/02225 ,  H01L29/41725 ,  H01L29/42312

Abstract: PURPOSE: A semiconductor device and a forming method thereof are provided to improve the low noise property by reducing the parasitic capacitance among the gate electrode, the source electrode, and the drain electrode. CONSTITUTION: An active layer is formed on the top of the substrate. The capping layer is formed on the active layer. A source and a drain electrode are formed on the capping layer. A gate electrode(140) is formed on the active layer. A first void region(155) is formed on the first side wall of the gate electrode. A second void region(156) is formed on the second side wall facing the first side wall.

Abstract translation: 目的：提供一种半导体器件及其形成方法，通过减小栅电极，源电极和漏电极之间的寄生电容来改善低噪声特性。 构成：在衬底的顶部上形成有源层。 覆盖层形成在有源层上。 源极和漏极形成在封盖层上。 在有源层上形成栅电极（140）。 第一空隙区域（155）形成在栅电极的第一侧壁上。 在面向第一侧壁的第二侧壁上形成第二空隙区域（156）。

公开(公告)号：KR1020100060108A

公开(公告)日：2010-06-07

申请号：KR1020080118554

申请日：2008-11-27

Applicant: 한국전자통신연구원

Inventor： 김해천 ,  강동민 ,  지홍구 ,  안호균 ,  문재경 ,  임종원 ,  장우진 ,  김동영 ,  이상흥 ,  유현규 ,  남은수

IPC: H01L27/04 ,  H01L29/772

Abstract: PURPOSE: A method for manufacturing a pseudomorphic high electron mobility transistor device is provided to satisfy wideband characteristics and unconditionally stable conditions by including a negative feedback circuit. CONSTITUTION: In a method for manufacturing a pseudomorphic high electron mobility transistor device, an epitaxial substrate is provided(101). A source and a drain are formed on a substrate. The epitaxial substrate is processed by a gate recess etching including a dry and wet method to form a recess region. The gate(180) is formed in the recess region.

Abstract translation: 目的：提供一种用于制造伪像高电子迁移率晶体管器件的方法，通过包括负反馈电路来满足宽带特性和无条件稳定条件。 构成：在制造假晶高电子迁移率晶体管器件的方法中，提供外延衬底（101）。 源极和漏极形成在衬底上。 通过包括干法和湿法的栅极凹槽蚀刻来处理外延衬底以形成凹陷区域。 门（180）形成在凹陷区域中。

公开(公告)号：KR1020100060107A

公开(公告)日：2010-06-07

申请号：KR1020080118553

申请日：2008-11-27

Applicant: 한국전자통신연구원

Inventor： 장우진 ,  문재경 ,  지홍구 ,  안호균 ,  임종원 ,  강동민 ,  김동영 ,  이상흥 ,  김해천 ,  남은수

IPC: H03F1/30 ,  H03F3/189

CPC classification number: H03F3/193 ,  H03F1/0211 ,  H03F1/301 ,  H03F1/56 ,  H03F2200/451

Abstract: PURPOSE: A super high frequency amplifier and a bias circuit for the same are provided to optimize performance by adjusting a source voltage, regardless of a change in the properties of a depletion-type FET(Field Effect Transistor) due to the process change. CONSTITUTION: An amplifier circuit amplifies a high frequency signal through a depletion-type FET(30). An input matching circuit(20) matches the inputted high frequency signal in the depletion-type FET. An output matching circuit(40) matches the amplified signal, and thereby outputs the matched signal. A bias circuit(80) gives a negative value to a voltage between a gate and a source of the depletion-type FET by applying a positive voltage to the source of the depletion-type FET. The bias circuit tunes the voltage between the gate and the source by changing the positive voltage applied to the source.

Abstract translation: 目的：提供超高频放大器和偏置电路，以通过调节源极电压来优化性能，而不管由于过程变化而导致的耗尽型FET（场效应晶体管）的特性变化。 构成：放大器电路通过耗尽型FET（30）放大高频信号。 输入匹配电路（20）匹配耗尽型FET中输入的高频信号。 输出匹配电路（40）匹配放大的信号，从而输出匹配信号。 偏置电路（80）通过向耗尽型FET的源极施加正电压来给出耗尽型FET的栅极和源极之间的电压的负值。 偏置电路通过改变施加到源极的正电压来调节栅极和源极之间的电压。

公开(公告)号：KR100801570B1

公开(公告)日：2008-02-11

申请号：KR1020060122144

申请日：2006-12-05

Applicant: 한국전자통신연구원

Inventor： 장우진 ,  유현규 ,  김해천

IPC: H03F3/189

CPC classification number: H03F1/56 ,  H01P1/2135 ,  H03F3/193 ,  H03F3/604

Abstract: A UHF(Ultra High Frequency) amplifier is provided to minimize variation of a capacitance due to variation of a manufacturing condition by maintaining a constant capacitance irrespective of a thickness variation of a dielectric material. An amplifier amplifies a high frequency signal. Input matching circuits(110,130) match the high frequency signals from input terminals with each other and supply the matched signals to the amplifier. Bias supply units(150,160,170,180) supply bias voltages to the amplifier. Output matching circuits(120,135) deliver the high frequency signal amplified at the amplifier to an output terminal. A DC block/RF(Radio Frequency) matching unit(101,126,136) is coupled between the input terminal and the input matching circuit or between the output matching circuit and the output terminal, and is configured to have first and second strip lines having a spiral or curved shape.

Abstract translation: 提供UHF（超高频）放大器，以通过保持恒定的电容来最小化由于制造条件的变化引起的电容变化，而与电介质材料的厚度变化无关。 放大器放大高频信号。 输入匹配电路（110,130）将来自输入端子的高频信号彼此匹配，并将匹配的信号提供给放大器。 偏置电源单元（150,160,170,180）向放大器提供偏置电压。 输出匹配电路（120,135）将放大器放大的高频信号传送到输出端。 DC块/ RF（射频）匹配单元（101,126,136）耦合在输入端子和输入匹配电路之间或耦合在输出匹配电路和输出端子之间，并且被配置为具有第一和第二带状线，其具有螺旋形或 弯曲的形状。

公开(公告)号：KR1020070059842A

公开(公告)日：2007-06-12

申请号：KR1020060044929

申请日：2006-05-19

Applicant: 한국전자통신연구원

Inventor： 문재경 ,  조경익 ,  김해천 ,  장우진 ,  임종원 ,  지홍구 ,  안호균

IPC: C25D5/54

CPC classification number: C25D7/123 ,  C25D5/10 ,  C25D5/505

Abstract: A gold bump structure which can reduce defective proportion generated due to causes such as lead opening and the like in a process of bonding the gold bump to semiconductor chips and so on by improving non-uniformity of the gold bump with respect to thickness of a gold bump formed by a plating process, and a fabrication method of the gold bump structure are provided. A gold bump comprises: a seed metal layer formed on a substrate; a plating bump layer formed on an upper portion of the seed metal layer; and a domed gold-rich process alloy formed on an upper portion of the plating bump layer and made from a metal with a low melting point. A fabrication method of a gold bump comprises the steps of: forming a seed metal layer(23) on a substrate(21); plating and forming a gold bump layer(25) on the seed metal layer; forming a metal layer with a low melting point on the gold bump layer; and forming a domed gold-rich process alloy(27) on an upper portion of the low melting point metal layer-formed gold bump layer. The method further comprises the steps of: forming an adhesion layer(22) between the seed metal layer and the substrate; removing the exposed seed metal layer and the adhesion layer under the exposed seed metal layer; and forming a photosensitive film for forming patterns of the gold bump layer.

Abstract translation: 一种金凸块结构，其可以通过改善金凸块相对于金的厚度的不均匀性，从而在金凸块与半导体芯片等接合的过程中减少由于诸如引线开口等原因而产生的不良比例 提供通过电镀工艺形成的凸块，以及金凸块结构的制造方法。 金凸块包括：形成在基板上的种子金属层; 形成在种子金属层的上部的电镀突起层; 以及形成在电镀凸块层的上部并由具有低熔点的金属制成的穹顶金富余工艺合金。 金凸块的制造方法包括以下步骤：在基底（21）上形成种子金属层（23）; 电镀并在种子金属层上形成金突起层（25）; 在金凸点层上形成具有低熔点的金属层; 以及在低熔点金属层形成的金凸块层的上部形成圆顶状富金合金（27）。 该方法还包括以下步骤：在种子金属层和基底之间形成粘合层（22）; 去除暴露的种子金属层下的暴露的种子金属层和粘附层; 以及形成用于形成金凸块层的图案的感光膜。

公开(公告)号：KR100631051B1

公开(公告)日：2006-10-04

申请号：KR1020050084755

申请日：2005-09-12

Applicant: 한국전자통신연구원

Inventor： 임종원 ,  안호균 ,  지홍구 ,  장우진 ,  문재경 ,  김해천

IPC: H01L29/778

Abstract: A method for manufacturing a pseudo morphic high electro mobility transistor is provided to improve the electric property and to increase breakdown voltage by forming a passivation layer having double recess structure. A cap layer(24) and a channel layer(22) are formed on a substrate(20). A source/drain(26) is formed on the cap layer. A first passivation layer(27) is formed, and then patterned to expose the cap layer in a channel region. A first recess structure is formed by removing the exposed cap layer. A second passivation layer is formed on the entire surface of the resultant structure. A second recess structure is formed by patterning the second passivation layer(29) to expose the substrate of the first recess structure. A multi-layered photosensitive film is formed, and then patterned to have an opening of gate shape and to expose the substrate through the second recess structure. A gate is formed to connect to the substrate through the second recess structure by removing the multi-layered photosensitive film, after depositing a metal on the resultant structure.

Abstract translation: 提供了一种用于制造拟态高电动迁移率晶体管的方法，以通过形成具有双凹陷结构的钝化层来改善电特性并增加击穿电压。 盖层（24）和沟道层（22）形成在衬底（20）上。 源极/漏极（26）形成在盖层上。 形成第一钝化层（27），然后将其图案化以暴露沟道区中的盖层。 通过去除暴露的盖层来形成第一凹陷结构。 在所得结构的整个表面上形成第二钝化层。 通过图案化第二钝化层（29）以暴露第一凹陷结构的衬底来形成第二凹陷结构。 形成多层光敏膜，然后将其图案化以具有栅极形状的开口并通过第二凹陷结构暴露衬底。 在将金属沉积在所得结构上之后，通过去除多层光敏膜，形成栅极以通过第二凹陷结构连接到基板。

公开(公告)号：KR1020060061628A

公开(公告)日：2006-06-08

申请号：KR1020040100422

申请日：2004-12-02

Applicant: 한국전자통신연구원

Inventor： 지홍구 ,  김해천 ,  임종원 ,  문재경 ,  장우진 ,  안호균

IPC: H03F3/189

CPC classification number: H03F3/193 ,  H03F1/0266 ,  H03F1/56 ,  H03G1/0029

Abstract: 본 발명은 안정화 회로가 구비된 고주파 증폭기에 관한 것으로, 보다 상세하게는 소정의 고주파 신호를 증폭하기 위한 트랜지스터를 포함하는 고주파 증폭기에 있어서, 상기 트랜지스터의 입력단에 입력된 고주파 신호의 이득 손실을 방지함과 아울러 이득 안정도를 증가시키기 위한 저항과 캐패시터가 병렬로 구성된 안정화 회로가 직렬로 연결됨으로써, 고주파 증폭기의 이득 손실 없이 안정도를 향상시킬 수 있는 효과가 있다.
고주파 증폭기, 안정화 회로, 저항, 캐패시터, 임피던스, 트랜지스터, 입력 임피던스 정합부, 출력 임피던스 정합부, 바이어스 회로부