公开(公告)号：FI891784A0

公开(公告)日：1989-04-14

申请号：FI891784

申请日：1989-04-14

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G06F

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：DE69421453D1

公开(公告)日：1999-12-09

申请号：DE69421453

申请日：1994-05-25

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：SG44436A1

公开(公告)日：1997-12-19

申请号：SG1996000370

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGULA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：DE69030688D1

公开(公告)日：1997-06-19

申请号：DE69030688

申请日：1990-06-11

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F13/364

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：IN177313B

公开(公告)日：1996-12-28

申请号：IN628DE1989

申请日：1989-07-13

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

IPC: G06F7/00

公开(公告)号：IN177067B

公开(公告)日：1996-10-26

申请号：IN604DE1990

申请日：1990-06-20

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  MILLING PHILIP EDWARD

IPC: H04N1/00

公开(公告)号：FI96145C

公开(公告)日：1996-05-10

申请号：FI891786

申请日：1989-04-14

Applicant: IBM

Inventor： MILLING PHILIP ERNA ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

公开(公告)号：DE68923403T2

公开(公告)日：1996-03-07

申请号：DE68923403

申请日：1989-03-03

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：PT90632B

公开(公告)日：1995-12-29

申请号：PT9063289

申请日：1989-05-23

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  BEGUN RALPH M ,  DEAN MARK E

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：FI95971B

公开(公告)日：1995-12-29

申请号：FI891784

申请日：1989-04-14

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G06F12/00 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.