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    72.
    发明专利
    未知

    公开(公告)号：DE102004041331B4

    公开(公告)日：2007-05-10

    申请号：DE102004041331

    申请日：2004-08-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JAKOBS ANDREAS ,  GREGORIUS PETER

    IPC: G11C7/00 ,  H03M7/00

    Abstract: A code driver is described having a codeword source, which has n>1 source terminals and is designed to output at these terminals a sequence of n-digit codewords, each in the form of n parallel code characters, and having n parallel transmission paths between the n source terminals and n transmit terminals for sending the message represented by the codewords to a receiver. According to the invention, a selection device is provided, which indicates explicitly for each codeword which of the n digits of the codeword concerned are relevant to the decoding of the message in the receiver, and which, dependent on this explicit indication, activates only those of the n transmission paths that are assigned to the relevant digits of the codeword.

    74.
    发明专利
    未知

    公开(公告)号：DE102006019423A1

    公开(公告)日：2007-03-15

    申请号：DE102006019423

    申请日：2006-04-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WALLNER PAUL ,  SCHLEDZ RALF ,  GREGORIUS PETER ,  RUCKERBAUER HERMANN

    IPC: G06F12/00 ,  G11C7/10

    Abstract: A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

    76.
    发明专利
    未知

    公开(公告)号：DE102006000632A1

    公开(公告)日：2006-08-17

    申请号：DE102006000632

    申请日：2006-01-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER

    IPC: G11C7/10 ,  G11C7/22

    Abstract: One embodiment of the present invention provides a memory device comprising an array of memory cells, a control logic for writing data to and reading data from the array of memory cells, the control logic comprising a first interface, an input/output section for exchanging data, address and control signals with a circuit external to the memory device, the input/output section comprising a second interface for sending signals to and receiving signals from the first interface of the control logic, and a synchronizing facility connected to the first interface of the control logic and to the second interface of the input/output section for synchronizing the first interface of the control logic and the second interface of the input/output section.

    77.
    发明专利
    未知

    公开(公告)号：DE102005042269A1

    公开(公告)日：2006-04-13

    申请号：DE102005042269

    申请日：2005-09-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G11C7/22

    Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

    78.
    发明专利
    未知

    公开(公告)号：DE102004037163A1

    公开(公告)日：2006-03-23

    申请号：DE102004037163

    申请日：2004-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER

    IPC: H03L7/081 ,  G11C11/4063

    Abstract: A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.

    79.
    发明专利
    未知

    公开(公告)号：DE50201238D1

    公开(公告)日：2004-11-11

    申请号：DE50201238

    申请日：2002-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  HANNEBERG ARMIN

    IPC: H04L25/08 ,  H04L25/20

    Abstract: The invention relates to a transmitter for transmission of digital data via a transmission line ( 10 ), comprising a current-driving digital/analogue converter ( 1 ) which is arranged at the input of the transmitter; a current-operated form filter ( 2 ) for forming the current pulses which are supplied from the digital/analogue converter; a line driver ( 5 ) which carries out current/voltage conversion; and a circuit for offset compensation ( 6 ), which is arranged in a feedback path ( 11 ). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.

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