公开(公告)号：DE10334841B4

公开(公告)日：2006-12-21

申请号：DE10334841

申请日：2003-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/311 ,  H01L21/334 ,  H01L29/94

公开(公告)号：DE102005022840B3

公开(公告)日：2006-09-28

申请号：DE102005022840

申请日：2005-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  FITZ CLEMENS ,  DUPONT AUDREY

IPC: H01L21/283 ,  H01L21/8242

Abstract: The method involves forming an isolation layer (1) on the top surface of a semiconductor substrate, and then forming contact openings (2) by stripping the cell field area of the isolation layer. Dopants, which can be activated at high temperature, are implanted into the semiconductor substrate within the range of the contact openings. The dopants are activated for annealing the crystal defects on the semiconductor substrate. A metallic layer and coating layers are then formed on the semiconductor substrate. The contact openings are then annealed and filled with conductive material.

公开(公告)号：DE10149199B4

公开(公告)日：2006-05-18

申请号：DE10149199

申请日：2001-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  SCHLOESSER TILL

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/02

公开(公告)号：DE102004027356A1

公开(公告)日：2005-12-29

申请号：DE102004027356

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS

IPC: H01L21/8234 ,  H01L27/088

Abstract: Production of an integrated switching circuit comprises forming a layer stack formed by a dielectric layer (21) and a gate layer (22) on the substrate (10), removing the gate layer between doping regions (23) to form a trench structure (24) within the gate layer, and depositing a metallic layer on the gate layer to contact the doping regions in an electrically conducting manner. An independent claim is also included for: an integrated switching circuit produced using the above process.

公开(公告)号：DE102005005327A1

公开(公告)日：2005-12-15

申请号：DE102005005327

申请日：2005-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS

IPC: H01L21/335 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/085 ,  H01L29/745

Abstract: In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas, and which stress them accordingly, are provided in the semiconductor substrate in addition to the active areas formed by sections of a semiconductor substrate. The insulator structures are respectively established on a base section by which a tensile stress is induced in adjacent active areas. Insulator structures respectively next to a p-type FET are selectively provided with additional buffer layers by which, due to production, a compressive stress is induced in adjacent structures. The charge carrier mobility is increased both for electrons I n the channel regions of the n-type FETs and for holes in the channel regions of the p-type FETs, and the functionality is improved both for the n-type FETs and for the p-type FETs.

公开(公告)号：DE10321496A1

公开(公告)日：2004-12-16

申请号：DE10321496

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS ,  BIRNER ALBERT ,  KUDELKA STEPHAN

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/08

Abstract: The production of a trench capacitor comprises forming a trench (10) in a semiconductor substrate (1) using a hard mask (5), partially masking the upper trench region using a masking layer on the substrate, forming an insulating collar (25) on the substrate outside of the trench region, removing the collar on the substrate in the lower trench region using a mask (30), forming a capacitor dielectric (50) on the exposed substrate in the lower trench region, forming a first insulating filler (60) in the trench up to the collar in the lower and middle trench region below the masked upper trench region, selectively removing the masking layer on the upper trench region, and forming a trench contact made from a second conducting filler (70) on the first conducting filler in the trench below the upper side of the collar to contact a connecting region (KB).

公开(公告)号：DE10321466A1

公开(公告)日：2004-12-16

申请号：DE10321466

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

公开(公告)号：DE10207131A1

公开(公告)日：2003-08-28

申请号：DE10207131

申请日：2002-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANGER DIRK ,  GOLDBACH MATTHIAS

IPC: G03C5/00 ,  G03F1/00 ,  H01L21/033

Abstract: A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches-for instance for trench capacitors-the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask.

公开(公告)号：DE10162900C1

公开(公告)日：2003-07-31

申请号：DE10162900

申请日：2001-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  SELL BERNHARD ,  BIRNER ALBERT ,  GOLDBACH MATTHIAS

IPC: H01L21/288 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: The invention relates to a method for fabricating low-resistance electrodes in trench capacitors, and includes steps of: providing a wafer; producing trenches in the wafer; introducing the wafer into an electrolyte solution including a salt of an electrically conductive material; and electrically contact-connecting the wafer and applying a voltage between the wafer and a counterelectrode configured in the electrolyte solution to electrodeposit at least sections of the electrically conductive material in the trenches. The electrodeposition of the electrode material enables a uniform layer thickness along all regions of the trench wall.

公开(公告)号：DE10142591A1

公开(公告)日：2003-03-27

申请号：DE10142591

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  BIRNER ALBERT

IPC: H01L21/334 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242

Abstract: An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to be formed, in particular, a base region thereof. At least part of the widened region is then provided with a material region for the insulation region.